MK20DN512 FB_TA pin shared with FB_BE_7_0 -- any way around this?

[glester]

I recently put this question to Freescale support but they were unable to answer it.  It's a long shot at best, but here's the question . .

We have a design in which the K20 must access, via FlexBus, a remote DRAM which is connected to an FPGA.  Since the DRAM is shared with several video streams, and since therefore access times can vary considerably, we are obliged to use the FB_TA input to control bus transactions.  But we also need the byte enable signals so that the DRAM can be used by software in a normal manner.  The problem is that FB_TA and FB_BE_7_0 share the same package pin.

As we see it, there are 2 options for us:

1.  Connect FB_TA and access the DRAM as 32-bit words only; or

2.  Hook up the byte enables and use auto-acknowledge set up for the worst possible access time case (assuming it is within the auto-acknowledge range).

Neither option is satisfactory from our point of view.

Can you [i.e. anyone] suggest any other way in which we might achieve full byte-enabled FlexBus access with bus cycle termination controlled by the external device?

Thanks,

Gerry

[egoodii]

You should be able to (re)create byte-lane-enables in your FPGA from TSIZ1&0 (GROUP2&3) and Address 1&0, freeing GROUP5 for TA, and also GROUP4 (for burst? Is that the same info as TSIZ1/0=0b11?  So maybe CS2?).  The MPC823 bus has these general control signal characteristics, and section 13 (tables 13-2&3) of

http://cache.freescale.com/files/product/doc/MPC823UM.pdf?fpsp=1&WT_TYPE=Reference%20Manuals&WT_VEND...

can be useful, BUT note carefully the 'crazy' difference in the PowerPC architecture of numbering bits 0to31 'left to right' (A31=LSB) (and the MPC823 doesn't encode 'line burst' on TSIZ).

The old MC68040 bus is 'closer' and may be easier to identify with.  Section 7 (Table 7.1, Figure 7-4) of:

http://cache.freescale.com/files/32bit/doc/ref_manual/M68040UM.pdf?fpsp=1&WT_TYPE=Data%20Sheets&WT_V...