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RL(Read Latency) bit of EIM in i.MX6DL.

Question asked by Keita Nagashima on Dec 24, 2013
Latest reply on Nov 25, 2014 by Yuri Muhin

Dear Sir or Madam,

 

Refer to 22.9.4 Chip Select n Read Configuration Register 2 (EIM_CSnRCR2) in MCIMX6SDLRM(Rev.1).

[Q1]

Refer to RL bit.

Are "cycle" and EIM_clock the meaning?

 

[Q2]

RL bit can define "Feedback clock loop delay".

What is Feedback clock loop delay?

And, how should I set RL bit?

 

Keita

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