Etherent Problem Based On P2020E Processor

[baijack]

Hi all,

We designed board  based on the p2020e processor. And the etherent part of it is completely refered to the ethernet part of P2020RDB-PCA.

We got VSC7385 RGMII ethernet switch PHY connect to tsec1 port, AR8021 RGMII PHY connect to tsec3 port, and VSC8221 SGMII PHY connect to SERDES port. Exactly like P2020RDB-PCA.

All the design and peripheral circuit copy the reference design and double checked using P2020RM.

However,after power up, some problems came up with the ethernet part, describe as below:

1. Only SGMII port can work

2. RGMII port and ethernet switch port can not.

We checked all the possible power problem with it, it seems ok. We are sure there is no hardware problem. And we did flash the VSC7385 firmware of it and it work(after power up, the light of port went on).

Since only port can use is SGMII port that connect to the SERDES, we suspect both AR8021 RGMII PHY and VSC7385 ethernet switch PHY is not communicate with p2020 cpu. Or the eTSEC part of P2020 is not working.

Is there any tip about where we can check or any possible reason for this situation?

Thanks in advance.

Regards,

Bai

[yipingwang]

Please check the presence of the clocks EC_GTX_CLK125, GTX_CLK and RX_CLK.

Please check the following registers configuration according to P2020RM.

PORDEVSR

MACCFG1

MACCFG2

ECNTRL

Please check the MAC/PHY interface for the presence of data and validity of the protocol, please refer to table 14-933.

[baijack]

We checked the register according to table14-933 RGMII mode register initialization steps from P2020RM.

We found MACCFG2\ECNTRL\MACSTNADDR2 etc did not initialized. Still remains default value.

We suspect the initialzation sequence is not started or the whole eTSEC part is not working.

where should we check or set to fix this?

Thanks.

[baijack]

We double checked each clk signal.

EC_GTX_CLK125: We got a 100MHz clk signal.

TSEC1_RXCLK(connect to VSC7385): We got a 125MHz clk.

TSEC1_TXCLK(connect to VSC7385): none;

TSEC3_TXCLK(connect to AR8021): none;

TSEC3_RXCLK(connect to AR8021): none;

And we checked each register you said, in PORDEVSR the value was what we expected.

In MACCFG1,MACCFG2,ECNTRL the value are all set as default. Is there any important bit that we must set or it will not work? Or is there a standard value of such register on P2020RDB-PC that we can reference since we get the exactly same design of it?

And we try to use mw command in uboot to set some value of register above, it would not save after reset. How can we set such value permanently?

Thanks.

[yipingwang]

EC_GTX_CLK125 is the shared  clock source for the 125MHz reference clock for eTSEC1, eTSEC2, and eTSEC3. eTSEC1 and eTSEC2 also have configuration options to use the dedicated 125MHz reference clock source via TSEC1_TX_CLK and TSEC2_TX_CLK, respectively. Refer to GUTS_PMUXCR register in the P2020 reference manual for configuration options. Note: TSEC3 always uses EC_GTX_CLK125 for the 125Mhz reference clock.

Please refer to "14.4.1 eTSEC detailed signal descriptions" in P2020RM and the application note AN4261 probably would be helpful for you.

[baijack]

Thanks for your help.

We checked EC_GTX_CLK125, is ok. RX_CLK is ok. GTX_CLK is only available when some data is transmit, so it didn't shown.

Could you tell us how can we read such registers' value? It seems only have 5-byte offset address in P2020RM, we don't know where can we read/write such registers.

[yipingwang]

Please read these registers with "CCSRBAR+eTSEC offset address" in u-boot.

• eTSEC1 starts at 0x2_4000 address offset

• eTSEC2 starts at 0x2_5000 address offset

• eTSEC3 starts at 0x2_6000 address offset

Please refer to "14.5.2 eTSEC Memory Map/Register Definition" for details.

For example,

eTSEC2:

=> md ffe25000 4

[baijack]

Thanks for your reply.

So you mean on P2020RDB-PCA board, CCSRBAR address is 0xffe0_0000 and other CCSR register is based on ffe0_0000 and add offset address.

Is that right?

Happy holidays.

[yipingwang]

Yes, CCSRBAR is configured at 0xffe00000 in u-boot, you could refer to include/configs/P1_P2_RDB.h in u-boot source.