When configure the ddr memory map I can see that most of the configuration with 2x512MB density set CS0_END to 768 MB. If I set it to 512 MB that are logic I get some strange behavior when accessing higher addresses. Why should it be 768 MB!?
Is it possible to change CS1 start address or will it automatically start after CS0_END? If so than I cannot understand why 768 MB are used for CS0_END.