Dear Sir or Madam,
I have a question about EIM wait setting in i.MX6DL.
And I'd like to use the synchronous access on EIM.
[Q1]
Refer to EIM_CSnRCR1 field descriptions in MCIMX6SDLRM(Rev.1).
There is following description about RWSC(Read Wait State Control).
"start of an access"
Is it meaning of "The first rising-edge of BCLK"?
[Q2]
Refer to "Figure 22-12. SRD=1,BCD=0,BCS=0,RWSC=1,RADVA=0,RADVN=0,RFL=0,RL=0" in MCIMX6SDLRM(Rev.1).
When setting to RFL=1, where does the setting of RWSC correspond to in the Figure 22-12?
(It is difficult to understand Figure 22-12. It has mixed internal signal and external signals.)
[Q3]
Refer to Table 22-2 in MCIMX6SDLRM(Rev.1).
There is following description.
"NOTE: For burst devices, WAIT output should be configured to change one cycle before data is ready (before delay)"
This meaning is fixed 1 BCLK before data is ready, isn't it?
Keita
Solved! Go to Solution.
Please look at my comments below.
1.
> There is following description about RWSC(Read Wait State Control).
> "start of an access"
> Is it meaning of "The first rising-edge of BCLK"?
Correct.
2.
On the Figure 22-12 there are three BCLK cycles between data sampling
and start of the access. For RFL=1, RWSC indicates when the data is ready for
sampling by the EIM. This means data should be sampled at the rising edge of the
second cycle for RWSC=1. Really figure 22-12 shows diagram for RFL=0, that is, RWSC
bit field indicates when the EIM should start sampling WAIT (READY) signal. So three cycles
are as following : one cycle – start WAIT testing, one cycle - WAIT is OK (ready),
one cycle – read data.
3.
> "NOTE: For burst devices, WAIT output should be configured to change one cycle before data
> is ready (before delay)"
> This meaning is fixed 1 BCLK before data is ready, isn't it?
Yes.
Please look at my comments below.
1.
> There is following description about RWSC(Read Wait State Control).
> "start of an access"
> Is it meaning of "The first rising-edge of BCLK"?
Correct.
2.
On the Figure 22-12 there are three BCLK cycles between data sampling
and start of the access. For RFL=1, RWSC indicates when the data is ready for
sampling by the EIM. This means data should be sampled at the rising edge of the
second cycle for RWSC=1. Really figure 22-12 shows diagram for RFL=0, that is, RWSC
bit field indicates when the EIM should start sampling WAIT (READY) signal. So three cycles
are as following : one cycle – start WAIT testing, one cycle - WAIT is OK (ready),
one cycle – read data.
3.
> "NOTE: For burst devices, WAIT output should be configured to change one cycle before data
> is ready (before delay)"
> This meaning is fixed 1 BCLK before data is ready, isn't it?
Yes.