Flash ready bit of MDM-AP status reg. of the MKL05Z32 device

[Bajo]

Hi,

what does it mean when the Flash Ready bit of MDM-AP status register of MKL05Z32 is not set?

What can cause that this bit is not set? What shoul I do to get this bit set?

And one more question.

What is the correct mass erase procedure using MDM-AP control reg. (including the reset pin state and CortexM0+ debug registers)?

BR,

Jozef

[kerryzhou]

Hi Jozef,

     Thank you very much to create your question in our community!

     The Flash Ready bit of MDM-AP status register is not set means the flash has not been initialized, and it can't be accessed.

     Actually, if the chip is not damaged, after rational operation, this Flash Ready bit can be set.

     If your flash ready bit is not set, you should make sure whether your chip power voltage is higher than LVDH, you can't initialize the flash immediately after the power on.

     Besides the voltage, please following the SWD connection steps:

4.1.1 SWD connection steps

The recommended procedure for establishing a connection to the processor over SWD is listed below.

1. On devices that support EzPort, make sure that EZP_CS is high, so that SWD/JTAG pin functions are enabled.

2. Power on the processor, or if power has already been applied, assert the RESET pin to reset the processor. For devices

that do not have a RESET pin, write the System Reset Request bit in the MDM-AP control register after establishing

communication.

3. Keep reset low and establish communication with the ARM DAP. The MDM-AP ID register can be read to verify that

the connection is working correctly.

4. Read the MDM-AP status register until the Flash Ready bit sets.

5. Read the System Security bit to determine if security is enabled. If System Security = 0, then proceed. If System

Security = 1, then communication with the internals of the processor, including the flash, will not be possible without

issuing a mass erase command or unsecuring the part through other means (backdoor key unlock).

6. Write the MDM-AP register to set the Core Hold Reset bit. This will prevent the core from attempting to boot when the

reset pin is released. NOTE: the Core Hold Reset bit cannot be written if the processor is secured.

7. Negate the RESET signal or clear the System Reset Request bit in the MDM-AP control register.

When the steps above have been completed, debugging or flash programming can be started.

    About the details, please refer to our application notes in the attachment.

    About the mass erase procedure, please refer to the chapter 4.2 erasing flash in the AN 4835.

    Wish my answer helps you!

Best regards!

Jing

[Bajo]

Hi Jing,

it is now more clear to me, thanks for your support.

I have a question on Core Hold Reset bit in the MDM-AP control reg.. Does the "Core Hold Reset" bit halt the CPU core? Is the Core Halted bit its flag in the MDM-AP status reg.?

>When the steps above have been completed, debugging or flash programming can be started.

Does it mean, that the flash programming is possible when the Core is held in reset?

Best regards,

Jozef

[kerryzhou]

Hi Jozef,

1,    According to the definition of "Core Hold Reset" bit in reference manual, when this bit is 1, means: hold the core in reset at the end of reset sequencing, so it is not halt the CPU core.

   Halt means: Stopping of program execution due to a debug event (e.g., breakpoint or watchpoint), or due to user debug request. You can find the details from the arm core document" The definitive guide to the ARM cortex-M0"

2,>When the steps above have been completed, debugging or flash programming can be started

It doesn't means,that the flash programming is possible when the Core is held in reset?

because step 7:

7. Negate the RESET signal or clear the System Reset Request bit in the MDM-AP control register.

system reset request means: Set to force a system reset. The system remains held in reset until this bit is cleared.

So, when the system will not in reset, because already clear the "system reset request" bit.

Wish it helps you!

Best regards!

Jing