Section 31.4.5 Fast Flash Configuration for EDO has the following,
The NFC clock must be configured fast enough (usually > 33 MHz) according to the data sheet of flash devices.
On the IMX25, there are various timing diagrams which show how the NAND clock affect the timing. Originally, the NFC_CLK (from Chapter 10) was 133MHz with the main line Linux. I set this to 66MHz and the normal mode starts to function in EDO mode on the Tower board. However, when I turn on the ECC code it fails. I set the clock to 33Mhz and it is functioning. 9.12 Maximum Frequencies Supported has a maximum clocking of 80Mhz for the module. What kind of clock ranges does the module accept and are there timing diagrams so we can run a timing budget with our NAND chip selection and PCB traces?
19.4.3 Clocks at Boot Time has some timings that the boot code sets, but it never has the ECC enabled. Clocks are 30.85 (Normal Frequency) and 45.25 (Fast Frequency). It seems odd that all of the MTD tests pass without ECC and a 66MHz clock, but they fail with ECC enabled. The raw signals to the flash chip should be un-altered by the ECC; but I maybe running the NAND chip out of spec; how do I know? Is the clocking different when the module ECC is enabled?
In my case, I have a software ECC (Hamming, much like boot code) and all checks pass. There are other CRC32 data validations and no data or filesystem corruptions are observed with no hardware ECC and a 66MHz NFC clock. However, as soon as the hardware ECC is enabled, usually the 2nd 16bit value is corrupted unless the clock is change to ~33Mhz.