Hi Kinetis Team,
I'm experiencing some trouble with the 72 MHz Kinetis parts (MK20DX256VLH7, mask set 1N36B).
The problem appears as limited bus availability for DMA. In one extreme example, if I set up 2 DMA transfers to copy a fixed SRAM byte to the GPIO set and clear registers (triggered by edges on a PWM signal) and then place a "while (1) ;" infinite loop immediately after starting the DMA, no changes appear on the pin. But if I add 3 NOP instructions inside the loop, the DMA works and I see the pin toggle.
I found a workaround using "AXBS_PRS0 = 0x1032;". Assigning similar priorities to crossbar masters for SRAM and the GPIO bridge seems to make no difference, even though those are the 2 slave ports my DMA transfer should be using. It seems very strange that reassigning the priority on the slave port for flash memory would allow my DMA transfer to gain access to the SRAM and GPIO ports.
Maybe I've just misunderstood how all this works? The 50 MHz Kinetis didn't have any of this configuration and DMA always "just worked". Now on the 72 MHz parts, I'm seeing stalled DMA due to CPU activity that doesn't seem like it ought to conflict with the DMA accessing those other buses.
Thank you very much!