I make layout for custom design i.mx28 board. At the moment I'm trying to understand DDR layout rule.
In this document - http://www.freescale.com/files/32bit/doc/app_note/AN4215.pdf on page 9, describes rules are quite blurry.
So I found this document http://www.freescale.com/files/dsp/doc/app_note/AN3963.pdf page 9 describes all very clear but rules conflict with AN4215 document.
AN4215: Address and Command signals - length matched to each other within 200 mils
AN3963: Address and Bank - ≤ Clock length, Match the signals ± 20 mils
AN4215: Data signals - Lengths must be matched within 100 mils of the corresponding data strobes
AN3963: Data and Buffer - ≤ Clock length and Match the signals ± 20 mils or Max byte Group 1 length ≤ Clock length
What rules should be trusted?