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DDR layout question

Question asked by yar on Dec 16, 2013
Latest reply on Dec 16, 2013 by Peter Sinka

Hello,

I make layout for custom design i.mx28 board. At the moment I'm trying to understand DDR layout rule.

In this document - http://www.freescale.com/files/32bit/doc/app_note/AN4215.pdf on page 9, describes rules are quite blurry.

So I found this document http://www.freescale.com/files/dsp/doc/app_note/AN3963.pdf  page 9 describes all very clear but rules conflict with AN4215 document.


For example:


AN4215: Address and Command signals - length matched to each other within 200 mils

AN3963: Address and Bank - ≤ Clock length, Match the signals ± 20 mils



AN4215: Data signals - Lengths must be matched within 100 mils of the corresponding data strobes

AN3963: Data and Buffer - ≤ Clock length and Match the signals ± 20 mils or  Max byte Group 1 length ≤  Clock length


What rules should be trusted?

Thanks.





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