I have a question regarding the MPC5643L architecture. I saw
the reference manuals and the e200z4 data sheet too but
could not find this information. There is very little information
regarding the SRAM.
I enabled both the core of MPC5643L with both core
accessing the SRAM in their particular area. According to the
architecture of the Chip the processor cores share the SRAM
bus and must see a performance degradation. This is perhaps
not the case, the time to read for example a certain number of
32-bit word is same as when only one core access the RAM
instead of two. This tells that there is something in between
that is taking care of it.
(Note: I am not running the code from the Flash, I am running
the code from SRAM directly. We are using TRK-USB-
My other question is regarding the Instruction Cache. I tried
enabling the instruction cache by writing 3 to spr register
1011. Then inorder to evaluate the performance of the cache i
called few instructions in the code but I don't
see any difference in the timings with/without instruction
Note: (For this task also I directly download the code to the
SRAM and start executing it from there.)
If I am missing anything please let me know.