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SMPTE274 and SMPTE296 on i.mx6

Question asked by K R on Dec 12, 2013
Latest reply on Jan 10, 2014 by Yuri Muhin

Hello all,

    I am currently looking to output via the parallel interface of the i.mx6 the standards SMPTE274 and SMPTE296.


According to the reference manual (page 2699 of IMX6DQRM.pdf) the processor supports SMPTE274 and SMPTE296 in the parallel interface:


" Display Interface

The display interface is very flexible and supports a wide variety of devices from major

manufacturers. The following interface types are provided (in each of the two display


• Parallel video interface (for synchronous access) - up to 24-bit data bus.

  • Compatible with MIPI-DPI standard .

  • Control protocol - follows Sharp HR and generic TFT definitions

  • Supports BT.656 (8-bit) and BT.1120 (16-bit) protocols

  • Supports HDTV standards SMPTE274 (1080i/p) and SMPTE296 (720p)"


Also found in IMX6DQAE.pdf on page 99 it explains the ports, signals, and balls which both SMPTE standards can be output on.

I am looking to output the 20-bit format YCrCb.


The last column on the right side of Table 69 shows 20-bit YCrCb and the associated Port Names ('EDM Conn' refers to Wandboard):


Port Name                     EDM Conn Name           20-bit YCrCb        Ball

IPU1_DISP0_DAT00 -      DISP0_DAT0                     C[0]                P24 

IPU1_DISP0_DAT01 -      DISP0_DAT1                     C[1]                P22

IPU1_DISP0_DAT02 -      DISP0_DAT2                     C[2]                P23

IPU1_DISP0_DAT03 -      DISP0_DAT3                     C[3]                P21

IPU1_DISP0_DAT04 -      DISP0_DAT4                     C[4]                P20

IPU1_DISP0_DAT05 -      DISP0_DAT5                     C[5]                R25

IPU1_DISP0_DAT06 -      DISP0_DAT6                     C[6]                R23

IPU1_DISP0_DAT07 -      DISP0_DAT7                     C[7]                R24

IPU1_DISP0_DAT08 -      DISP0_DAT8                     C[8]                R22

IPU1_DISP0_DAT09 -      DISP0_DAT9                     C[9]                T25


IPU1_DISP0_DAT10 -      DISP0_DAT10                   Y[0]                R21

IPU1_DISP0_DAT11 -      DISP0_DAT11                   Y[1]                T23

IPU1_DISP0_DAT12 -      DISP0_DAT12                   Y[2]                T24

IPU1_DISP0_DAT13 -      DISP0_DAT13                   Y[3]                R20

IPU1_DISP0_DAT14 -      DISP0_DAT14                   Y[4]                U25

IPU1_DISP0_DAT15 -      DISP0_DAT15                   Y[5]                T22

IPU1_DISP0_DAT16 -      DISP0_DAT16                   Y[6]                T21 

IPU1_DISP0_DAT17 -      DISP0_DAT17                   Y[7]                U24

IPU1_DISP0_DAT18 -      DISP0_DAT18                   Y[8]                V25

IPU1_DISP0_DAT19 -      DISP0_DAT19                   Y[9]                U23

IPU1_DI0_DISP_CLK -     DI0_DISP_CLK                PixCLK             N19

IPU1_DI0_PIN02 -           DI0_PIN2                         HSYNC             N25

IPU1_DI0_PIN03 -           DI0_PIN3                         VSYNC             N20


The problem that arises is I have no clue how to setup the processor to do such. Could someone please point me in the right direction to register maps or the likes?

This help is greatly appreciated.


My current setup is a Wandboard with i.mx6 Quad running Yocto 1.5


Thanks for your help.