AnsweredAssumed Answered

IMX6 as PCIe endpoint : help requested

Question asked by Sylvain FABRE on Dec 9, 2013
Latest reply on Dec 17, 2013 by Sylvain FABRE
Branched to a new discussion

Thanks to the patches available here : i.MX6Q PCIe EP/RC Validation System , i can link 2 boards thru PCIe and write the RC memory.

But now, i need to convert the EP board into a real endpoint, with at least 1 MEM area and 1 IO area. This is done on the EP side with the proper BAR configuration, and the RC recognized it (seen with lspci -v and a custom kernel module). But up to now, i am unable to adress properly the IO BAR from the RC. I guess it is related to the iATU configuration for adresss translation, but my trials are failing up to now.

 

Shall i configure an inbound translation ? An outbound ? Both ?

 

Is there someone with a small piece of code showing the whole configuration used to declare/setup an IO space on a IMX6 and to access it from another IMX6 ?

 

Thanks, SF

Outcomes