AnsweredAssumed Answered

Kinetis KL05xx Problems with LPTMR or clock distribution

Question asked by Christian Fischer on Dec 3, 2013
Latest reply on Dec 6, 2013 by Hui_Ma

Hello to all,

 

at the moment we have started to get familiar with KL05xxx devices by using the Freescal Eval- Board.

Starting point are the sources devlievered with the evaluation package which was modfied for test reason.

 

Here the setup which we expect the system to work in:

 

- transit to BLBI mode (via FBI mode)

- start operating in VLPR- mode using fast internal reference clock of 4MHz

- use fast internal reference clock as input for MCGIRCLK to clock LPTMR timer which will toggle some GPIO

 

So far so good.

Bringing the system into VLPR is not the problem but now the trouble starts:

 

Wwe have recgonized is that it is impossible to get an output at the GPIO pins that are triggered by LPTMR higer then 30kHz (Bypass mode and Counter compare value = 0) when using Fast Internal Reference clock.

 

Regarding the clocking diagram the output frequency should be much higher, right ?

I also checked register values in MCG and system configuration but all of the values seems to be right. Status register MCG_S shows fast internal reference and everthing else seems to be okay as well. So what is the problem with that issue at the moment I have no idea, so any hint or advice is very welcomed.

 

Thanks for you help !!!!

 

Christian

 

Here you find the test code of the project:

------------------------------------------

int main (void)

{ WORD bcount =0;

    BYTE bHelp = FALSE;

    DWORD dwTempReg;

 

    MCG_C1 |= MCG_C1_IRCLKEN_MASK;

    lptmr_init(COUNT_VALUE,0);

      

        while(!(LPTMR0_CSR &  LPTMR_CSR_TCF_MASK));

 

        {

            LPTMR0_CSR |=  LPTMR_CSR_TCF_MASK;

            GPIOA_PTOR = 0x00000100;

             

        } 

 

    } 

and here how we init the system:

 

void sysinit (void)

{

        /* Enable all of the port clocks. These have to be enabled to configure

         * pin muxing options, so most code will need all of these on anyway.

         */

        SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK );

    

        // releases hold with ACKISO:  Only has an effect if recovering from VLLS1, VLLS2, or VLLS3

        // if ACKISO is set you must clear ackiso before calling pll_init

        //    or pll init hangs waiting for OSC to initialize

        // if osc enabled in low power modes - enable it first before ack

        // if I/O needs to be maintained without glitches enable outputs and modules first before ack.

        if (PMC_REGSC &  PMC_REGSC_ACKISO_MASK)

                {

                    PMC_REGSC |= PMC_REGSC_ACKISO_MASK;

                } 

             

#ifdef BOOTLOADER

       SIM_CLKDIV1 = ( 0

                        | SIM_CLKDIV1_OUTDIV1(0)      

                        | SIM_CLKDIV1_OUTDIV4(1) );

     

        dwMcgClkHz =  fee_32OSC();

        uart0_clk_khz = (dwMcgClkHz / 1000); // the UART0 clock frequency will equal the FLL frequency

#else

 

    

    

       /* Set the system dividers */

      //SIM_CLKDIV1 = ( 0

      //                  | SIM_CLKDIV1_OUTDIV1(0)        /*clockdivider for core /system clock* 1:1*/

      //                  | SIM_CLKDIV1_OUTDIV4(1) );    /*clockdivider for bus/ flash clock 1:4*/

 

 

      /*set clock mode*/

            /*transition from fei (reset condition) to fbi */         

      /* Set the system dividers */

      SIM_CLKDIV1 = ( 0

                        | SIM_CLKDIV1_OUTDIV1(0)        /*clockdivider for core /system clock* 1:1*/

                        | SIM_CLKDIV1_OUTDIV4(4) );    /*clockdivider for bus/ flash clock 1:4*/

 

            SIM_SOPT2  = (SIM_SOPT2_CLKOUTSEL(4)| SIM_SOPT2_TPMSRC(3));

         

            MCG_SC |= MCG_SC_FCRDIV(0);

            dwMcgClkHz = fei_fbi(4000000, FAST_IRC);

         

         

         

            /*transition from fei to blbi for low power application*/

            dwMcgClkHz = fbi_blpi(4000000, FAST_IRC);

      //MCG_SC |= MCG_SC_FCRDIV(FCRDIV_FACTOR_1);

            //MCG_C1 |= MCG_C1_IRCLKEN_MASK;

            //if (dwMcgClkHz < 0x100)

      //   while(1);

 

 

            /*

                    * Use the value obtained from the pll_init function to define variables

            * for the core clock in kHz and also the peripheral clock. These

            * variables can be used by other functions that need awareness of the

            * system frequency.

            */

      dwMcgClkKhz         = dwMcgClkHz         / 1000;

        dwCoreClkKhz         = dwMcgClkKhz     / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> 28)+ 1);

      dwPeriphClkKhz     = dwCoreClkKhz     / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> 16)+ 1);

     

             

         

            /*INIT GPIOs*/

        

         

            /*PORTB*/

            PORTB_GPCLR = 0xFFFF0143;/*All Ppins of Port B ar GPIOs*/

            PORTB_GPCHR = 0x00000000;

         

            GPIOB_PDDR    = 0x00000000; /*all Pins of Port B ar Inputs*/

         

            /*PORTA*/

            PORTA_GPCLR = 0xFF000143;/* Pins 3-16 of Port A ar GPIOs*/

            PORTA_GPCLR = 0x00050343;

            PORTA_GPCHR = 0x00000000;

         

            GPIOA_PDDR    = 0x00000F00; /*Portpins 8-11 of Port A ar outputs*/

         

            GPIOA_PDOR    = 0x00000000; /*init value*/ 

 

         

      

         

            /*power mode*/

            dwPwrStatus = enter_vlpr();

Outcomes