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Vybrid core clock setting

Question asked by Jeremy Esquirol on Nov 21, 2013
Latest reply on Nov 25, 2013 by Jeremy Esquirol

Hi !


I'm using a TWR-VF6xx with Embedded Linux on cortex-A5 core. It seems that the core clock is set to 396Mhz using PLL1_PFD3 (register value read with DS-5).

First, I don't understand where the core clock is initialized ? I've seen in file clock.c that all clocks are registered but the function :


int  __init mvf_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
// keep correct count
    pll1_sys_main_clk.usecount += 5;
    pll2_528_bus_main_clk.usecount += 5;

#if 0
    clk_set_parent(&periph_clk, &pll2_pfd2_396M);
    clk_enable(&periph_clk); /* platform bus clk */
    clk_enable(&ipg_clk); /* ips bus clk */


only enable pll3_usb_otg_main_clock ? Where are enabled the others?


Second, there are some vybrid specific function in this file, and my goal is just to set the core clock to 450Mhz. I just modify the .parent of the PLL1_SW_CLK by PLL1_PFD2_450M using the function

static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)

but it seems that has no effect. Is anyone can help me?