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K20 i2c master bug?

Question asked by Marc Lindahl on Nov 19, 2013
Latest reply on Dec 12, 2013 by Hui_Ma

I'm debugging a K20F120 board and running into a problem where the 9th SCL is not issued, somewhere in the middle of transferring (block write) several tens of KB, usually after several hundred bytes.

 

I noticed the same bug mentioned here: i2c: Is This a Bug?

 

I'm attaching a logic analyzer capture, where I set the cursors at the ACK bit of the previous two bytes.  You can see the spike on SDA but it's within timing requirements, it's a valid ACK.  So then you can count the Kinetis is only issuing 8 bytes the last time (analyzer set to trigger on a both-low timeout), so the slave has no chance to ACK.

 

Slowing down the overal timing doesn't help.  Putting  big waits between bytes doesnt help.  Doing one byte at a time doesn't help.  Tried setting the glitch filter to 3, that didn't help.  Eventually this happens....

 

Bug?  Workaround? 

 

Thx

MarcIMG_2708.JPG.jpg

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