I have a protoype board for VF3x. I am using DS-5 and MQX to test it. Since MQX is prepared for tower kit, the core clock is set to 399 MHz in clocks.init() in init_hw.c file, as below:
// wait to lock pll
while ((Anadig_PLL_LOCK & PLL_LOCKS) != PLL_LOCKS);
// ARM_CLK: SYS_CLK/1 = 396Mhz
// BUS_CLK: ARM_CLK/3 = 132Mhz
// IGP_CLK: BUS_CLK/2 = 66Mhz
// AUDIO_DIV: 73Mhz ??
CCM_CACRR = CCM_CACRR_ARM_CLK_DIV(0) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_PLL4_CLK_DIV(7);
There are definitions for the CCM_CACRR_ARM_CLK_DIV() in MVF50GS10MK50.h file as:
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7u
#define CCM_CACRR_ARM_CLK_DIV_SHIFT 0
#define CCM_CACRR_ARM_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_ARM_CLK_DIV_SHIFT))&CCM_CACRR_ARM_CLK_DIV_MASK)
But it is not easy to reach a result from this line for me. How can I set the core frequency to 266 MHz? ( I guess it is the maximum frequency for VF3x)
Thanks and best regards.
Mehmet Ali Ipin