Mikhail Burakov

Wrong clock configuration in FLEXCAN_Initialize

Discussion created by Mikhail Burakov on Nov 14, 2013
Latest reply on Nov 27, 2013 by Mikhail Burakov

Hello community!


I've noticed strange behavior in FLEXCAN_Initialize. No matter what you pass as the last argument (clock source), this option is never applied. I performed a small investigation and found the reason for this. Prior to actually setting the clock source, softreset is issued to flexcan (kflexcan.c:325):

   if((can_reg_ptr->MCR & CAN_MCR_MDIS_MASK) == 0x00000000)
      /* clock disable (module) */
      can_reg_ptr->MCR = CAN_MCR_MDIS_MASK;


      /* wait until disable mode acknowledged */
      while (!can_reg_ptr->MCR & CAN_MCR_LPMACK_MASK) {}


   /* Reset FLEXCAN, Halt, freeze mode */
      return (FLEXCAN_INIT_FAILED);
   /*  Wait for entering the freeze mode */
   while((can_reg_ptr->MCR & CAN_MCR_FRZACK_MASK) == 0) {}
   ** Select the clock source
   ** Default: internal bus clock (fsys/2).
   FLEXCAN_Select_clk (dev_num, clk);


In the FLEXCAN_Softreset, flexcan leaves "module disable" state. But according to K20 Sub-Family Reference Manual, clock source bit (CLKSRC of CANx_CTRL1) can be modified only in "module disable" state (p. 1112).



Best regards,

Mikhail Burakov