I cannot understand the relations of FB_TA and the state of the bus cycle.
When auto-acknowledge disable ( AA = 0 ) ,
does it continue the current state (S1) until FB_TA becomes Low ?
If FB_TA becomes Low, is it changed by the next state (S2) ?
Yes, your understanding is correct.
If FB_TA is recognized asserted(driven low internally or externally), then the cycle moves on to S2. If FB_TA is not asserted internally or externally, then the S1 state continues to repeat.
Hope that makes sense,
Thank you for answer.
Another one point let me ask you a question.
Is the following description a mistake?
in "Freescale Semiconductor Document Number: AN4393 Application Note Rev. 0, 05/2012"
2.1 Read cycle
"If the auto-acknowledge feature is disabled (CSCRn[AA] = 0), then FB_TA must be negated 13.5 ns (FB4) before the third cycle."
I think the above description means if you want to put the FlexBus into next stage, FB_TA must be negated 13.5 ns (FB4) before the third cycle when auto-acknowledge feature is disabled.
Thank you for your answer.
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