When running bare metal code on the i. MX6 Solo I always get a software interrupt. UBOOT tells me the reset cause is WDOG. How do I fix this?

[kyleengstrom]

This is my second time posting this. Last discussion went dead. And why does the last one say "Assumed Answered." ? I couldn't figure how to take that off even though this was not answered at all!

This is how I reset the watchdog timer in my baremetal code.

Freescale i.MX6SOLO rev1.1

static void watchdog_reset(void)

       {

    watchdog_reg_p base = (watchdog_reg_p) WDOG1_BASE_ADDR;

    /* Init Watchdog */

    base->wcr = WCR_WDA | WCR_SRS | WCR_WT | WCR_WDBG;

    /*enable watchdog */

    base->wcr |= WCR_WDE;

    base->wsr = 0x5555;

    base->wsr = 0xAAAA;

    }

Uboot gives me this when I try and run my code.

U-Boot > fatload usb 0:1 0x12000000 testme.axf

fatload usb 0:1 0x12000000 testme.axf

reading testme.axf

95376 bytes read in 57 ms (1.6 MiB/s)

U-Boot > bootelf

bootelf

## Starting application at 0x00900000 ...

software interrupt

pc : [<00903a28>]   lr : [<00903a28>]

sp : 0093efe0  ip : 0093e010 fp : 00904a60

r10: 00904a60  r9 : 2f359f38 r8 : 2f35b9a0

r7 : 00904a4f  r6 : 00000000 r5 : 00000000  r4 : 00000000

r3 : 00000000  r2 : 0093e000 r1 : 00000000  r0 : 00000010

Flags: nzCv  IRQs off  FIQs off  Mode SVC_32

Resetting CPU ...

resetting ...

U-Boot 2013.10-rc4-00124-g2c62998 (Oct 14 2013 - 14:45:57)

CPU:   Freescale i.MX6SOLO rev1.1 at 792 MHz

Reset cause: WDOG

I can see that the program runs till it hits location 903a28 before being stopped with a software interrupt. I believe that uboot turns off the watchdog timer on the i.MX6. Does anything look weird here? How should I move forward debugging this? We are trying to run bare metal applications on the i.MX6 Solo without using the debugger tools. What is the best way to accomplish this? Uboot seems to work fine we just keep getting this software interrupt.

Oh and the I'm using

U-Boot 2013.10-rc4-00124-g2c62998 (Oct 14 2013 - 14:45:57)

Thank you so much for any help!

Best regards.

[AnsonHuang]

Hi, Kyle

     I think you use uboot to run your elf, and it caused an exception, and in ./arch/arm/lib/interrupts.c, the "bad_mode" function call reset_cpu(0);, for our i.MX6 SoC, we implement the reset_cpu(0) as below, so it is a wdog reset, I think you may need to debug your elf test case, it should not generate a software interrupt, this is my understanding.

drivers/watchdog/imx_watchdog.c:

54 void reset_cpu(ulong addr)

55 {

56         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

57

58         writew(WCR_WDE, &wdog->wcr);

59         writew(0x5555, &wdog->wsr);

60         writew(0xaaaa, &wdog->wsr);     /* load minimum 1/2 second timeout */

61         while (1) {

62                 /*

63                  * spin for .5 seconds before reset

64                  */

65         }

66 }