In our application, the K60 is an I2C slave on two different I2C buses. We are seeing some odd timing with the setup time of the data signal compared to the rising edge of the clock when both bus are active. Has anyone figured out what the slave baud rate control, bit 4 of I2C Control Register 2 does? We are not sure what the master baud rate refers to in the description, either the I2C Frequency Divider Register or the I2C bus master clock rate. Should bit 4 of I2C Control Register 2 be set or not? It seems that the configuration of the I2C Frequency Divider Register effects the data setup time.