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Does the KL26 digital outputs continue to drive output pins in all the various Stop sleep modes?

Question asked by nurichard on Nov 7, 2013
Latest reply on Nov 15, 2013 by nurichard



The rev 3.2 October 2013 KL26 Sub-Family Reference Manual KL26P121M48SF4RM states in table 7-2 (pg 161) that the GPIO module goes into the following conditions in the various stop sleep modes:

Stop: static output, wakeup input / Fully functional in PSTOP2

VLPS: static output, wakeup input

LLS: static, pins latched

VLLS: OFF, pins latched


Q1) Is this telling me that the GPIO module registers will retain their values except in VLLS (where it is OFF)?


As there is no entry in this table for the PORT control (described in chapter 11), does this mean that it continues to operate the same as it does in run mode, even in all VLLS modes?

My particular interests are in confirming that:

Q2) the outputs continue to be driven with the same strength as in run mode?

Q3) input pull-ups / pull-downs continue to operate as in run mode?

Q4) will the PORT registers retain their values in all modes?

Q5) does an output pin continue to be low or high when changing between any mode?


Thank you all for your help,