Need spec for ENET_REF_CLK and PCI_E clock(CLK1_P/N) in MX6Q

[jim_lin]

Hello,

can't find the detailed requirement for the follow two clock: 1. ENET_REF_CLK, 2. PCI_E clock supplied from CLK1_P/CLK1_N.

Need the following information for reference:

OSC/125MHz for ENET_REF_CLK (#V22) : VIH 、VIL、Tolerance 、High time、 Low time、Rise time 、Falling time 、Jitter

PCIE/100MHz for CLK1_P/N (#C7,#D7) : Duty cycle、Tolerance、Rise time 、Falling time 、Jitter、Voltage swing

The information is required to choose the right components when composing the schematics.

Thank you,

Jim.

[Yuri]

Please use the Hardware Development Guide for i.MX6.

< http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf >

According to section 2.7 (Oscillator tolerance) it is recommended using the official (RMII, PCIe)

specifications. We can refer to Table 2-20 (24 MHz crystal tolerance

guidelines)  of the Development Guide, assuming stability (thermal, voltage and

other) of PLL output clock is fully defined by external crystal / oscillator,

and i.MX6  meets USB, PCIe, Ethernet clock specs.

  Also, please refer to i.MX6 RMII timing specs in corresponding Datasheets.