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K60 ethernet problem when using FLL

Question asked by James Elliot on Oct 31, 2013
Latest reply on Nov 11, 2013 by Zhe Tian

Hi

 

I'm using a K60 revision 2 and what I'm trying to do is run the chip from the RTC oscillator. I have apparently managed to achieve this, but the problem comes when the ethernet is involved, I set the R flag on a TX buffer to indicate that the K60 should send the frame, and the flag never gets cleared.

 

I'm using a PK60DN512VLK10 2N22D

 

The board has two clocks, a 50MHz on EXTAL and 32.768KHz on EXTAL32. Prior to the revision 2 it wasn't possible to use the RTC oscillator to drive the FLL so I have been using the 50MHz signal and generating a 96MHz PLL for the core clock, then setting the dividers to get a 48MHz bus and 24MHz flash. I have the dividers the same on the FLL so as far as I know everything is running at the same speed.

 

Are there any issues that I should be aware about when changing from a PLL to FLL? Hypothetically if I did have it running at a slower speed than what the PLL is running at, why would this effect the TX buffer?

 

Thanks

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