Is it possible to use the Vybrid observation clock outputs (CKO1, CKO2) for clocking another chip?
Yes, you may use these clocks for another chip; if not a secret, what kind of application is it - audio, Ethernet, DSP, etc.? - The reason I am asking is that some applications requite really high-quality (i.e low-jitter) clock.
Feel free to call me and discuss these details if required (BTW, I speak Russian fluently).
Best regards, Naoum Gitnik.
Hardware Systems and Applications Engineer
6501 W. William Cannon Dr.
Austin, TX 78735
Thanks for the answer! It really helps.
I plan to use CKO1 to clock a Bluetooth module with Vybrid's 32.768 kHz RTC clock. The Bluetooth module is a part of a hardware that is designed by another company so all I know at the moment about requirements for this clock is just -/+100ppm accuracy. I guess that the accuracy should be satisfied with +/-20 ppm external 32.768kHz resonator.
Is it possible to know any jitter related parameters of the CKOx outputs?
Я не уверен, что телефонный звонок будет удобней, чем обсуждение здесь, т.к. между Москвой и Остином большая разница во времени. Но всё равно, спасибо за предложение).
You are welcome; let's continue communicating in writing then.
Based on the Reference Manual, you indeed may use CKO2 to bring the SXOSC (Slow external crystal oscillator) clock out - see the '10.2.14 CCM Clock Output Source Register (CCM_CCOSR)' register, 'CKO2_SEL' bit group for details.
Regarding the clock quality required for your Bluetooth device:
1. Yes, the -/+100 ppm frequency accuracy requirement does not look extraordinary and difficult to meet,
2. More critical, though, is the jitter requirement, and It looks like you have not finalized it yet, right?
Unfortunately, the outputs of interest are considered auxiliary ("observation"...), i.e. used for debugging only, hence not characterized.
At the same time, it works in your favor (a lot!) that you are going to take this clock 'as is' from the oscillator, i.e. without altering its frequency by passing through a PLL, so the only noise acquired (inside the processor, take care of this on the board as well) while traveling to the CKO2-bearing IO pin is that coupled from adjacent die signals, which is lower than that added by a PLL.
BTW, even with a PLL, based on my experience for another project, in which a processor had to generate special-frequency audio clock for a CODEC, measured already on the CODEC input, with heavy computations running on the processor (video-streaming application), the jitter value for ~24MHz audio clock was ~70ps. I realize this is a different application but good enough to let you get a taste of a worst-case scenario. Again, in your application, a lot of factors are working in your favor, and chances of having no problems are very high.
Best regards, Naoum Gitnik.
P.S. In my previous "reincarnation", I've lived between the Sviblovo subway and Losinoostrovskaya (Losinka) railroad stations .
Thank you for additional valuable information.
I hope to get your advise on a possiblity of using the CKO2 output when I get the jitter requirements.
P.S. I live on the other end of the city, in Chertanovo. But several years ago I was working not far from your place, near Botanichesky Sad station on Selskohozjaistvennaja street. I had several colleagues from Losinka. I bet you wouldn't recognize this place now..
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