Kristof Geldhof

irregular ADC read-out

Discussion created by Kristof Geldhof on Jul 31, 2007
Latest reply on Aug 3, 2007 by Pascal Irrle

I downloaded the hands-on exercise PWM_ADC_SYN (synchronization of ADC with PWM) from the freescale website. As a test, I applied a constant voltage of 1.5V to the ADC input pin ANA0. However, successive ADC conversions (and scaling) give results that are scattered around the correct value. This means, the mean value of the measurements corresponds to the 1.5V, but there are deviations of approximately 10%. The applied voltage is constant (checked it with a scope). The internal VREFHI and VREFLO voltages (3.3V and GND respectively, used as reference voltages by the ADC) are also constant. What could be the reason of these bad read-outs?

Thanks in advance for any help.

Kristof Geldhof