Since the NFC and FlexBus pins are shared, there is an internal arbiter that controls which peripheral has access to those pins. This arbiter can be configured using the SIM_SOPT6 register, with the PCR and MCC fields. The bit descriptions for PCR and MCC in the Reference Manual are lacking in detail. The functions of these bits in Kinetis are similar to the MCF5441x device (copied from MCF5441x Reference Manual):
PCR - Post-cycle reservation
Specifies the length of the FlexBus post-cycle reservation period in internal bus clock cycles.
0x0 or 0x1 No post-cycle reservation, and the arbiter returns to the idle loop as soon as the FlexBus is no longer busy.
0x2 or more Enables post-cycle reservation
MCC - Minimum consecutive cycles.
Specifies the minimum amount of time in internal bus clock cycles provided by the arbiter for NAND flash activity. At least MCC internal bus clock cycles must elapse before a FlexBus request is recognized, and the NFC may, in fact, use the shared pins for more than MCC internal bus clock cycles absent such a request. A value of 0 makes the arbiter respond immediately to a FlexBus request and pause the NFC as soon as possible.
