Bruce, the Freescale RM covers the MCU in detail, the core is only superficially documented there because there is already in-depth documentation for the core provided by ARM here:
http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php
And in the ARM Infocenter:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439c/I1010015.html
To your exact question:
Cortex M0+ cores have a 32 x 32 = 32 multiply that can be a single cycle or a 32-cycle implementation, Freescale uses the single-cycle implementation.
Bruce, the Freescale RM covers the MCU in detail, the core is only superficially documented there because there is already in-depth documentation for the core provided by ARM here:
http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php
And in the ARM Infocenter:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439c/I1010015.html
To your exact question:
Cortex M0+ cores have a 32 x 32 = 32 multiply that can be a single cycle or a 32-cycle implementation, Freescale uses the single-cycle implementation.
Hello,I also have some problems in using the one cycle 32X32 multiplier of Cortex M0+.The MCU I'm using is MKE02Z16VLC2,and the bus clock is 20MHz,I have tested that
a int32Xint32 operation takes 10us,and a int32/int16 takes 14us,is there anything wrong or I haven't used it correctly?
When I use the DSC MC56F8013,there are many functions such as 'mult_r()' which can be used to optimize the program,is there something similar here?
Best Regards!
kinetis L is based on cotex M0+ core. so it can use MULS
instruction to execute multiply in a single cycle
Yes, ARM have it as an option on the M0+, and I can't find it specified in the KL25Z documentation, however there are plenty of references to the fast bit-banging, which is also an option.
tks