is there anything I need to do with the DDR controller after it has caused a data abort through accessing non existent addresses? It seems happy on writes, but seems to give a data abort on reads.
According to the i.MX6 Reference Manual :
“The following registers in the MMDC define the DDR address space:
• MDMISC[DDR_4_BANK]—Defines either 4 or 8 banks in the DDR device
• MDCTL[DSIZ]—Defines the DDR data bus width of x16, x32 or x64
• MDMISC[BI]—Defines whether bank interleaving is on or off
• MDCTL[COL]—Defines the column size of the DDR device
• MDCTL[ROW]—Defines the row size of the DDR device”.
Also, “It is optional to configure the partition between the chip selects through
Generally for an access to an address, which is not used (non-covered) by internal i.MX6 modules, we can expect ARM data abort exception, but the following
statement (NOTE) may be considered as recommendation to avoid such accesses :
“In cases where this is an access to a non-initialized or disconnected chip select,
behavior may be unexpected”.
If it is required to define memory size – it makes sense to test it without checking
addresses, that are out of range. It is enough to test (quite accessible) memory region
via writing and consequent reading data, assuming they are equal for real memory.
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