Hi,
I'm having a strange problem on a P5020 processor.
In fact core0 is generating IVOR6 0x0700 exception "ESR register showing illegal instruction exception" on a simple printf while core1 as no problem running and is on the exact same TLC configuration script.
The TCL was modified in ord to use CPC1 and CPC2 as SDRAM.
The DDR controller 1 and 2 are separatly mapped by 2 LAW's each of 2 GB.
TLB entries were made for each too.
/******************************************************************
************************** MAIN ********************************/
int main()
{
nt i=0;
unsigned long proc_id;
asm ("mfpir %0" : "=r" (proc_id));
#if SMPTARGET
initSmp();
#endif
printf("Core%d: printf de test !\r\n", proc_id>>5);
//asm("sc"); // generate a system call exception to demonstrate the ISR
return 0;
}
Problem solved.
Used init_sram.tcl for CPC SRAM configuration. (thanks to marius viorel grigoras, it was very helpfull for setting the SRAM mode of the CPC)
Remapped the DDR to 0x0000_0000 -> 3FFF_FFFF which is 1GB in size with DDR1 512MB and DDR2 512MB.
- DDR controllers not interleaved.
- Banks not interleabed in each DDR.
CPC1 and CPC2 are map from 0x4000_0000 to 0x401F_FFFF 1MB each.
Cache L2 disable
Cache L1 data disable
Cache L1 instruction enable.
DDR configuration was the main problem, caution during configuration is the main solution.
Cheers.
Thanks for sharing your final integration solution!
Regards,
Marius
Builded a new configuration and i'm trying to turn off the interleaving mode of the DDR controllers.
My goal is to have 2GB of menory managed by DDR controller 1 and 2 other GB of memory managed by controller 2.
There is 2 DRR dimms on my card, each of 2gb. (running cpu's at 2.0Ghz and DDR at 1333Mhz)
What would be the best configuation for DDR registers, LAW's and TLB's to achieve this ?
Tested CPC1, CPC2, Dissableling cache L2 and L1 data and it had no problems running simple code.
But when it comes to configure the DDR controllers I get data tlb miss or machine check exceptions.
Any help is appreciated.
Thanks.
Sorry miss clicked and the post was sent..
Here is the TCL scrip used.
Any help would be appreciated !
########################################################################################
# Initialization file for P5020 DS
# Clock Configuration:
# CPU0:2000 MHz, CPU1:2000 MHz, CCB: 800 MHz,
# DDR: 1333 MHz, SYSCLK: 133 MHz, LBC: 100 MHz
########################################################################################
variable master_core 0
variable CCSRBAR 0xFE000000
proc CCSR {reg_off} {
global CCSRBAR
return i:0x[format %x [expr {$CCSRBAR + $reg_off}]]
}
proc init_board {} {
# disable Boot Space Translation
# LCC_BSTAR
mem [CCSR 0x28] = 0x00000000
# invalidate again BR0 to prevent flash data damage in case
# the boot sequencer re-enables CS0 access
# LCC_BSTAR
mem [CCSR 0x124000] = 0x00001000
##################################################################################
# Local Access Windows Setup
# LAW0 to eLBC (NOR) - 256M
# LAW_LAWBARH0
mem [CCSR 0xC00] = 0x00000000
# LAW_LAWBARL0
mem [CCSR 0xC04] = 0xE0000000
# LAW_LAWAR0
mem [CCSR 0xC08] = 0x81F0001B
# LAW1 to BMAN - 2MB
# LAW_LAWBARH1
mem [CCSR 0xC10] = 0x00000000
# LAW_LAWBARL1
mem [CCSR 0xC14] = 0xF4000000
# LAW_LAWAR1
mem [CCSR 0xC18] = 0x81800014
# LAW2 to QMAN - 2MB
# LAW_LAWBARH2
mem [CCSR 0xC20] = 0x00000000
# LAW_LAWBARL2
mem [CCSR 0xC24] = 0xF4200000
# LAW_LAWAR2
mem [CCSR 0xC28] = 0x83C00014
# LAW3 to eLBC (PIXIS) - 4KB
# LAW_LAWBARH3
mem [CCSR 0xC30] = 0x00000000
# LAW_LAWBARL3
mem [CCSR 0xC34] = 0xFFDF0000
# LAW_LAWAR3
mem [CCSR 0xC38] = 0x81F0000B
# LAW4 to DCSR - 4MB
# LAW_LAWBARH4
mem [CCSR 0xC40] = 0x00000000
# LAW_LAWBARL4
mem [CCSR 0xC44] = 0xF0000000
# LAW_LAWAR4
mem [CCSR 0xC48] = 0x81D00015
# LAW5 to PEX1 - 512MB
# LAW_LAWBARH5
# mem [CCSR 0xC50] = 0x00000000
# LAW_LAWBARL5
# mem [CCSR 0xC54] = 0x80000000
# LAW_LAWAR5
# mem [CCSR 0xC58] = 0x8000001C
# LAW6 to PEX1 - 64KB
# LAW_LAWBARH6
mem [CCSR 0xC60] = 0x00000000
# LAW_LAWBARL6
mem [CCSR 0xC64] = 0xF8000000
# LAW_LAWAR6
mem [CCSR 0xC68] = 0x8000000F
# LAW7 to PEX2 - 512MB
# LAW_LAWBARH7
mem [CCSR 0xC70] = 0x00000000
# LAW_LAWBARL7
mem [CCSR 0xC74] = 0xA0000000
# LAW_LAWAR7
mem [CCSR 0xC78] = 0x8010001C
# LAW8 to PEX2 - 64KB
# LAW_LAWBARH8
mem [CCSR 0xC80] = 0x00000000
# LAW_LAWBARL8
mem [CCSR 0xC84] = 0xF8010000
# LAW_LAWAR8
mem [CCSR 0xC88] = 0x8010000F
# LAW9 to PEX3 - 512MB
# LAW_LAWBARH9
mem [CCSR 0xC90] = 0x00000000
# LAW_LAWBARL9
mem [CCSR 0xC94] = 0xC0000000
# LAW_LAWAR9
mem [CCSR 0xC98] = 0x8020001C
# LAW10 to PEX3 - 64KB
# LAW_LAWBARH10
mem [CCSR 0xCA0] = 0x00000000
# LAW_LAWBARL10
mem [CCSR 0xCA4] = 0xF8020000
# LAW_LAWAR10
mem [CCSR 0xCA8] = 0x8020000F
# LAW11 to eLBC (NAND) - 1M
# LAW_LAWBARH11
mem [CCSR 0xCB0] = 0x00000000
# LAW_LAWBARL11
mem [CCSR 0xCB4] = 0xF8200000
# LAW_LAWAR11
mem [CCSR 0xCB8] = 0x81F00013
# LAW31 to Interleaved DDR - 2GB
# LAW_LAWBARH31
# mem [CCSR 0xDF0] = 0x00000000
# LAW_LAWBARL31
# mem [CCSR 0xDF4] = 0x00000000
# LAW_LAWAR31
# mem [CCSR 0xDF8] = 0x8140001E
#ajout
# LAW28 CPC1 1MB 0x8000_0000
# LAW_LAWBARH28
mem [CCSR 0xDC0] = 0x00000000
# LAW_LAWBARL28
mem [CCSR 0xDC4] = 0x80000000
# LAW_LAWAR28
mem [CCSR 0xDC8] = 0x81000013
# LAW29 CPC2 1MB 0x8010_0000
# LAW_LAWBARH29
mem [CCSR 0xDD0] = 0x00000000
# LAW_LAWBARL29
mem [CCSR 0xDD4] = 0x80100000
# LAW_LAWAR29
mem [CCSR 0xDD8] = 0x81100013
# LAW30 DDR1 | 0x00000000 - 0x0_8000_0000 | 2GB
# LAW_LAWBARH31
mem [CCSR 0xDE0] = 0x00000000
# LAW_LAWBARL31
mem [CCSR 0xDE4] = 0x00000000
# LAW_LAWAR31
mem [CCSR 0xDE8] = 0x8100001E
# LAW31 DDR2 | 0x1_0000_0000 - 0x1_8000_0000 | 2GB
# LAW_LAWBARH31
# mem [CCSR 0xDF0] = 0x00000001
# LAW_LAWBARL31
# mem [CCSR 0xDF4] = 0x00000000
# LAW_LAWAR31
# mem [CCSR 0xDF8] = 0x8110001E
##################################################################################
# DDR Controllers Setup - the names are from the new drop but the registers
# are from the old drop
# DDR1_DDR_SDRAM_CFG
mem [CCSR 0x8110] = 0x47044000
# DDR1_CS0_BNDS
mem [CCSR 0x8000] = 0x000000ff
# DDR1_CS1_BNDS
mem [CCSR 0x8008] = 0x00000000
# DDR1_CS0_CONFIG
mem [CCSR 0x8080] = 0x80014202
# DDR1_CS1_CONFIG
mem [CCSR 0x8084] = 0x80014202
# DDR1_CS0_CONFIG_2
mem [CCSR 0x80C0] = 0x00000000
# DDR1_CS1_CONFIG_2
mem [CCSR 0x80C4] = 0x00000000
# DDR1_TIMING_CFG_3
mem [CCSR 0x8100] = 0x00020000
# DDR1_TIMING_CFG_0
mem [CCSR 0x8104] = 0x50110104
# DDR1_TIMING_CFG_1
mem [CCSR 0x8108] = 0x6f6b4644
# DDR1_TIMING_CFG_2
mem [CCSR 0x810C] = 0x0fa888cc
# DDR1_DDR_SDRAM_CFG_2
mem [CCSR 0x8114] = 0x24401001
# DDR1_DDR_SDRAM_MODE
mem [CCSR 0x8118] = 0x00441420
# DDR1_DDR_SDRAM_MODE_2
mem [CCSR 0x811C] = 0x00000000
# DDR1_DDR_SDRAM_MODE_3
mem [CCSR 0x8200] = 0x00001420
# DDR1_DDR_SDRAM_MODE_4
mem [CCSR 0x8204] = 0x00000000
# DDR1_DDR_SDRAM_MODE_5
mem [CCSR 0x8208] = 0x00001420
# DDR1_DDR_SDRAM_MODE_6
mem [CCSR 0x820C] = 0x00000000
# DDR1_DDR_SDRAM_MODE_7
mem [CCSR 0x8210] = 0x00001420
# DDR1_DDR_SDRAM_MODE_8
mem [CCSR 0x8214] = 0x00000000
# DDR1_DDR_SDRAM_MD_CNTL
mem [CCSR 0x8120] = 0x00000000
# DDR1_DDR_SDRAM_INTERVAL
mem [CCSR 0x8124] = 0x0c300100
# DDR1_DDR_DATA_INIT
mem [CCSR 0x8128] = 0xdeadbeef
# DDR1_DDR_SDRAM_CLK_CNTL
mem [CCSR 0x8130] = 0x02800000
# DDR1_DDR_INIT_ADDR
mem [CCSR 0x8148] = 0x00000000
# DDR1_DDR_INIT_EXT_ADDRESS
mem [CCSR 0x814C] = 0x00000000
# DDR1_TIMING_CFG_4
mem [CCSR 0x8160] = 0x00000001
# DDR1_TIMING_CFG_5
mem [CCSR 0x8164] = 0x02401400
# DDR1_DDR_ZQ_CNTL
mem [CCSR 0x8170] = 0x89080600
# DDR1_DDR_WRLVL_CNTL
mem [CCSR 0x8174] = 0x8675f606
# DDR1_DDR_WRLVL_CNTL_2
mem [CCSR 0x8190] = 0x00000000
# DDR1_DDR_WRLVL_CNTL_3
mem [CCSR 0x8194] = 0x00000000
# DDR1_DDR_SR_CNTR
mem [CCSR 0x817C] = 0x00000000
# DDR1_DDRCDR_1
mem [CCSR 0x8B28] = 0x80000000
# DDR1_DDRCDR_2
mem [CCSR 0x8B2C] = 0x00000000
# DDR1_ERR_SBE
mem [CCSR 0x8E58] = 0x00000000
# DDR2_DDR_SDRAM_CFG
mem [CCSR 0x9110] = 0x47044000
# DDR2_CS0_BNDS
mem [CCSR 0x9000] = 0x000000ff
# DDR2_CS1_BNDS
mem [CCSR 0x9008] = 0x00000000
# DDR2_CS0_CONFIG
mem [CCSR 0x9080] = 0x80014202
# DDR2_CS1_CONFIG
mem [CCSR 0x9084] = 0x80014202
# DDR2_CS0_CONFIG_2
mem [CCSR 0x90C0] = 0x00000000
# DDR2_CS1_CONFIG_2
mem [CCSR 0x90C4] = 0x00000000
# DDR2_TIMING_CFG_3
mem [CCSR 0x9100] = 0x00020000
# DDR2_TIMING_CFG_0
mem [CCSR 0x9104] = 0x50110104
# DDR2_TIMING_CFG_1
mem [CCSR 0x9108] = 0x6f6b4644
# DDR2_TIMING_CFG_2
mem [CCSR 0x910C] = 0x0fa888cc
# DDR2_DDR_SDRAM_CFG_2
mem [CCSR 0x9114] = 0x24401111
# DDR2_DDR_SDRAM_MODE
mem [CCSR 0x9118] = 0x00441420
# DDR2_DDR_SDRAM_MODE_2
mem [CCSR 0x911C] = 0x00000000
# DDR2_DDR_SDRAM_MODE_3
mem [CCSR 0x9200] = 0x00001420
# DDR2_DDR_SDRAM_MODE_4
mem [CCSR 0x9204] = 0x00000000
# DDR2_DDR_SDRAM_MODE_5
mem [CCSR 0x9208] = 0x00001420
# DDR2_DDR_SDRAM_MODE_6
mem [CCSR 0x920C] = 0x00000000
# DDR2_DDR_SDRAM_MODE_7
mem [CCSR 0x9210] = 0x00001420
# DDR2_DDR_SDRAM_MODE_8
mem [CCSR 0x9214] = 0x00000000
# DDR2_DDR_SDRAM_MD_CNTL
mem [CCSR 0x9120] = 0x00000000
# DDR2_DDR_SDRAM_INTERVAL
mem [CCSR 0x9124] = 0x0c300100
# DDR2_DDR_DATA_INIT
mem [CCSR 0x9128] = 0xdeadbeef
# DDR2_DDR_SDRAM_CLK_CNTL
mem [CCSR 0x9130] = 0x02800000
# DDR2_DDR_INIT_ADDR
mem [CCSR 0x9148] = 0x00000000
# DDR2_DDR_INIT_EXT_ADDRESS
mem [CCSR 0x914C] = 0x00000000
# DDR2_TIMING_CFG_4
mem [CCSR 0x9160] = 0x00000001
# DDR2_TIMING_CFG_5
mem [CCSR 0x9164] = 0x02401400
# DDR2_DDR_ZQ_CNTL
mem [CCSR 0x9170] = 0x89080600
# DDR2_DDR_WRLVL_CNTL
mem [CCSR 0x9174] = 0x8675f606
# DDR2_DDR_WRLVL_CNTL_2
mem [CCSR 0x9190] = 0x00000000
# DDR2_DDR_WRLVL_CNTL_3
mem [CCSR 0x9194] = 0x00000000
# DDR2_DDR_SR_CNTR
mem [CCSR 0x917C] = 0x00000000
# DDR2_DDRCDR_1
mem [CCSR 0x9B28] = 0x80000000
# DDR2_DDRCDR_2
mem [CCSR 0x9B2C] = 0x00000000
# DDR2_ERR_SBE
mem [CCSR 0x9E58] = 0x00000000
# delay before enable
wait 500
# DDR1_DDR_SDRAM_CFG
mem [CCSR 0x8110] = 0xe7044000
# DDR2_DDR_SDRAM_CFG
mem [CCSR 0x9110] = 0xe7044000
# wait for DRAM data initialization
wait 1500
##################################################################################
# eSPI Setup
# ESPI_SPMODE
mem [CCSR 0x110000] = 0x80000403
# ESPI_SPIM - catch all events
mem [CCSR 0x110008] = 0x00000000
# ESPI_SPMODE0
mem [CCSR 0x110020] = 0x30170008
##################################################################################
# LBC Controller Setup
# CS0 - NOR, addr at 0xE8000000, 128MB size, 16-bit, GCPM, Valid
# eLBC_BR0
mem [CCSR 0x124000] = 0xe8001001
# eLBC_ORg0
mem [CCSR 0x124004] = 0xf8000f85
# CS1 - PromJet, addr at 0xE0000000, 128MB size, 16-bit, GCPM, Valid
# eLBC_BR1
mem [CCSR 0x124008] = 0xe0001001
# eLBC_ORg1
mem [CCSR 0x12400C] = 0xf8000ff7
# CS2 - NAND, addr at 0xF8200000, 256KB size, 8-bit, FCM, Valid
# eLBC_BR2
mem [CCSR 0x124010] = 0xF8200C21
# eLBC_ORf2
mem [CCSR 0x124014] = 0xFFFF87CC
# CS3 - PIXIS, addr at 0xFFDF0000, 1MB size, 8-bit, GCPM, Valid
# eLBC_BR3
mem [CCSR 0x124018] = 0xffdf0801
# eLBC_ORg3
mem [CCSR 0x12401C] = 0xffff8ff7
#ajout
# CS4 - NAND, addr at 0xF8200000, 256KB size, 8-bit, FCM, Valid
#BR4 = 0xF8200C21
mem [CCSR 0x124020] = 0xF8200C21
#OR4 = 0xFFFF87CC
mem [CCSR 0x124024] = 0xFFFF87CC
# CS5 - NAND, addr at 0xF8200000, 256KB size, 8-bit, FCM, Valid
#BR5 = 0xF8200C21
mem [CCSR 0x124028] = 0xF8200C21
#OR5 = 0xFFFF87CC
mem [CCSR 0x12402C] = 0xFFFF87CC
# CS6 - NAND, addr at 0xF8200000, 256KB size, 8-bit, FCM, Valid
#BR6 = 0xF8200C21
mem [CCSR 0x124030] = 0xF8200C21
#OR6 = 0xFFFF87CC
mem [CCSR 0x124034] = 0xFFFF87CC
#fin ajout
# eLBC_LBCR
mem [CCSR 0x1240D0] = 0x40000000
# LCRR CLKDIV = 16
# eLBC_LCRR
mem [CCSR 0x1240D4] = 0x80000002
# eLBC_FMR
mem [CCSR 0x1240E0] = 0x0000F000
##################################################################################
# CoreNet Platform Cache 1
# configure internal CPC1 as SRAM
# CNetPC1_CPCSRCR0 - SRBARL=0, INTLVEN=0, SRAMSZ=0101, SRAMEN=1
mem [CCSR 0x10104] = 0x8000000B
# CPC_CPCSRCR1
mem [CCSR 0x10100] = 0x00000000
# CNetPC1_CPCEWCR0 - disable stashing
mem [CCSR 0x10010] = 0x00000000
# CNetPC1_CPCERRDIS
mem [CCSR 0x10E44] = 0x00000000
# CNetPC1_CPCERRINTEN
mem [CCSR 0x10E48] = 0x00000000
# CPC_CPCERRCTL
mem [CCSR 0x10E58] = 0x00ffffff
# No error injection
mem [CCSR 0x10E00] = 0x00000000
mem [CCSR 0x10E04] = 0x00000000
mem [CCSR 0x10E08] = 0x00000000
# No speculative memory access
mem [CCSR 0x10F00] = 0x08000000
# invalidate(CPCFI) and No flash lock clear(CPCLFC)
# CNetPC1_CPCCSR0
mem [CCSR 0x10000] = 0x00200400
wait 500
# enable L3 SRAM
# CNetPC1_CPCCSR0
mem [CCSR 0x10000] = 0x80000000
#CNerPC1_CPCCFG0
##################################################################################
# CoreNet Platform Cache 2
# configure internal CPC2 as SRAM
# CNetPC2_CPCSRCR0 - SRBARL=0, INTLVEN=0, SRAMSZ=0101, SRAMEN=1
mem [CCSR 0x11104] = 0x8010000B
# CPC2_CPCSRCR1
mem [CCSR 0x11100] = 0x00000000
# CNetPC2_CPCEWCR0 - disable stashing
mem [CCSR 0x11010] = 0x00000000
# CNetPC2_CPCERRDIS
mem [CCSR 0x11E44] = 0x00000000
# CNetPC2_CPCERRINTEN
mem [CCSR 0x11E48] = 0x00000000
# CPC2_CPCERRCTL
mem [CCSR 0x11E58] = 0x00ffffff
# No error injection
mem [CCSR 0x11E00] = 0x00000000
mem [CCSR 0x11E04] = 0x00000000
mem [CCSR 0x11E08] = 0x00000000
# No speculative memory access
mem [CCSR 0x11F00] = 0x08000000
# invalidate(CPCFI) and No flash lock clear(CPCLFC)
# CNetPC2_CPCCSR0
mem [CCSR 0x11000] = 0x00200400
wait 500
# enable L3 SRAM
# CNetPC2_CPCCSR0
mem [CCSR 0x11000] = 0x80000000
##################################################################################
# Serial RapidIO - enable timeouts such that cores can be stopped succesfully
# set timers to max values
# SRIO_PLTOCCSR
mem [CCSR 0xC0120] = 0xFFFFFF00
# SRIO_PRTOCCSR
mem [CCSR 0xC0124] = 0xFFFFFF00
# SRIO_P1LOPTTLCR
mem [CCSR 0xD0124] = 0xFFFFFF00
# SRIO_P2LOPTTLCR
mem [CCSR 0xD01A4] = 0xFFFFFF00
# set all bits
# SRIO_P1ERECSR
mem [CCSR 0xC0644] = 0x007E0037
# SRIO_P2ERECSR
mem [CCSR 0xC0684] = 0x007E0037
}
proc P5020DS_init_core_cacheon {} {
##################################################################################
#
# Memory Map
#
# 0x00000000 0x7FFFFFFF DDR1 2G
# ##0x80000000 0x9FFFFFFF PEX1 512M##
# 0x80000000 0x80100000 CPC1 1M
# 0x80000000 0x80100000 CPC2 1M
# 0xA0000000 0xBFFFFFFF PEX2 512M
# 0xC0000000 0xDFFFFFFF PEX3 512M
# 0xE0000000 0xEFFFFFFF LocalBus 256M
# 0xF0000000 0xF3FFFFFF DCSR 4M
# 0xF4000000 0xF41FFFFF BMAN 2M
# 0xF4200000 0xF43FFFFF QMAN 2M
# 0xF8000000 0xF800FFFF PEX1 I/O 64K
# 0xF8010000 0xF801FFFF PEX2 I/O 64K
# 0xF8020000 0xF802FFFF PEX3 I/O 64K
# 0xF8200000 0xF82FFFFF NAND 1M
# 0xFE000000 0xFEFFFFFF CCSR Space 16M
# 0xFFDF0000 0xFFDF0FFF PIXIS 4K
# 0xFFFFF000 0xFFFFFFFF Boot Page 4k
# 0x100000000 0x17FFFFFFF DDR2 2G
#
##################################################################################
##################################################################################
# MMU initialization
global master_core
variable CAM_GROUP "regPPCTLB1/"
variable SPR_GROUP "e5500 Special Purpose Registers/"
variable GPR_GROUP "General Purpose Registers/"
# define 16MB TLB entry 1 : 0xFE000000 - 0xFEFFFFFF for CCSR cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM1 = 0x7000000A1C08000000000000FE00000000000000FE000001
# define 256MB TLB entry 2 : 0xE0000000 - 0xEFFFFFFF for LB cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM2 = 0x9000000A1C08000000000000E000000000000000E0000001
# define 1GB TLB entry 3 : 0x80000000 - 0xBFFFFFFF for PEX1/2 cache inhibited, guarded
#reg ${CAM_GROUP}L2MMU_CAM3 = 0xA000000A1C08000000000000800000000000000080000001
# ajout, CPC1 cacheable + coherency
reg ${CAM_GROUP}L2MMU_CAM3 = 0x500000041C08000000000000800000000000000080000001
# define 256MB TLB entry 4 : 0xC0000000 - 0xCFFFFFFF for PEX3 cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM4 = 0x9000000A1C08000000000000C000000000000000C0000001
# define 256MB TLB entry 5 : 0xD0000000 - 0xDFFFFFFF for PEX3 cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM5 = 0x9000000A1C08000000000000D000000000000000D0000001
# define 256KB TLB entry 6 : 0xF8000000 - 0xF803FFFF for PEX I/0 cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM6 = 0x4000000A1C08000000000000F800000000000000F8000001
# define 1GB TLB entry 7 : 0x00000000 - 0x3FFFFFFF for DDR cacheable
reg ${CAM_GROUP}L2MMU_CAM7 = 0xA00000041C08000000000000000000000000000000000001
# define 1GB TLB entry 8 : 0x40000000 - 0x7FFFFFFF for DDR cacheable
reg ${CAM_GROUP}L2MMU_CAM8 = 0xA00000041C08000000000000400000000000000040000001
# define 1MB TLB entry 9 : 0xF4000000 - 0xF40FFFFF for BMAN cacheable
reg ${CAM_GROUP}L2MMU_CAM9 = 0x500000041C08000000000000F400000000000000F4000001
# define 1MB TLB entry 10 : 0xF4100000 - 0xF41FFFFF for BMAN cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM10 = 0x5000000A1C08000000000000F410000000000000F4100001
# define 1MB TLB entry 11 : 0xF4200000 - 0xF42FFFFF for QMAN cacheable
reg ${CAM_GROUP}L2MMU_CAM11 = 0x500000041C08000000000000F420000000000000F4200001
# define 1MB TLB entry 12 : 0xF4300000 - 0xF43FFFFF for QMAN cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM12 = 0x5000000A1C08000000000000F430000000000000F4300001
# define 4MB TLB entry 13 : 0xF0000000 - 0xF03FFFFF for DCSR cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM13 = 0x6000000A1C08000000000000F000000000000000F0000001
# define 4KB TLB entry 14 : 0xFFDF0000 - 0xFFDF0FFF for PIXIS cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM14 = 0x1000000A1C08000000000000FFDF000000000000FFDF0001
# define 1MB TLB entry 16 : 0xF8200000 - 0xF82FFFFF; for NAND, cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM16 = 0x5000000A1C08000000000000F820000000000000F8200001
#define 1MB TLB entry 15 : 0x8010_0000 for CPC2 cacheable + coherency
reg ${CAM_GROUP}L2MMU_CAM15 = 0x500000041C08000000000000801000000000000080100001
# init board, only when the init is run for master core
variable proc_id [expr {[reg ${SPR_GROUP}PIR %d -np] >> 5 }]
if {$proc_id == $master_core} {
init_board
}
##################################################################################
# Interrupt vectors initialization
# interrupt vectors in RAM at 0x[expr {${proc_id} << 2}]0000000
# IVPR (default reset value)
set Ret [catch {evaluate __start__SMP}]
if {$Ret} {
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 2}]0000000
} else {
# SMP project, same interrupt vectors for all cores
reg ${SPR_GROUP}IVPR = 0x00000000
}
# interrupt vector offset registers
# IVOR0 - critical input
reg ${SPR_GROUP}IVOR0 = 0x00000100
# IVOR1 - machine check
reg ${SPR_GROUP}IVOR1 = 0x00000200
# IVOR2 - data storage
reg ${SPR_GROUP}IVOR2 = 0x00000300
# IVOR3 - instruction storage
reg ${SPR_GROUP}IVOR3 = 0x00000400
# IVOR4 - external input
reg ${SPR_GROUP}IVOR4 = 0x00000500
# IVOR5 - alignment
reg ${SPR_GROUP}IVOR5 = 0x00000600
# IVOR6 - program
reg ${SPR_GROUP}IVOR6 = 0x00000700
# IVOR7 - floating point unavailable
reg ${SPR_GROUP}IVOR7 = 0x00000800
# IVOR8 - system call
reg ${SPR_GROUP}IVOR8 = 0x00000c00
# IVOR10 - decrementer
reg ${SPR_GROUP}IVOR10 = 0x00000900
# IVOR11 - fixed-interval timer interrupt
reg ${SPR_GROUP}IVOR11 = 0x00000f00
# IVOR12 - watchdog timer interrupt
reg ${SPR_GROUP}IVOR12 = 0x00000b00
# IVOR13 - data TLB errror
reg ${SPR_GROUP}IVOR13 = 0x00001100
# IVOR14 - instruction TLB error
reg ${SPR_GROUP}IVOR14 = 0x00001000
# IVOR15 - debug
reg ${SPR_GROUP}IVOR15 = 0x00001500
# IVOR35 - performance monitor
reg ${SPR_GROUP}IVOR35 = 0x00001900
# Doorbell
reg ${SPR_GROUP}IVOR36 = 0x00001200
###################################################################
# Enable caches
# L1 init: CFI, CE, ICFI, ICE
# reg ${SPR_GROUP}L1CSR0 = 0x00000003
# reg ${SPR_GROUP}L1CSR1 = 0x00000003
# ajout #############################
# desactive L1 dcache
reg ${SPR_GROUP}L1CSR0 = 0x00000002
# active L1 icache
reg ${SPR_GROUP}L1CSR1 = 0x00010001
#####################################
# L2 init: L2E, L2FI
# reg ${SPR_GROUP}L2CSR0 = 0x80200000
# ajout
# desactive L2 cache (unifie)
reg ${SPR_GROUP}L2CSR0 = 0x00000000
##################################################################################
# Enable branch prediction
# reg ${SPR_GROUP}BUCSR = 0x01400201
# ajout
# disable branch prediction
reg ${SPR_GROUP}BUCSR = 0x00000200
##################################################################################
# Debugger settings
# enable machine check
#reg ${SPR_GROUP}HID0 = 0x80000000
# ajout
# Enable machine check signal + L2MMU multihits detection
reg ${SPR_GROUP}HID0 = 0xc0000000
# enable floating point
reg ${SPR_GROUP}MSR = 0x00002000
# infinite loop at program exception to prevent taking the exception again
mem v:0x${proc_id}0000700 = 0x48000000
# prevent stack unwinding at entry_point/reset when stack pointer is not initialized
reg ${GPR_GROUP}SP = 0x000000000000000F
if {$proc_id == $master_core} {
# BRRL - enable all cores
# DCFG_BRR
mem [CCSR 0xE00E4] = 0x00000003
# CTBENL - enable all cores' timebase
# RCPM_CTBENR
mem [CCSR 0xE2084] = 0x00000003
}
}
proc envsetup {} {
# Environment Setup
radix x
config hexprefix 0x
config MemIdentifier v
config MemWidth 32
config MemAccess 32
config MemSwap off
}
#-------------------------------------------------------------------------------
# Main
#-------------------------------------------------------------------------------
envsetup
P5020DS_init_core_cacheon
Hi,
First of all can you tell me please why you need such a configuration?
What you need in your program? Full DDR working, SRAM configuration...or DDR+cache activated?
I'm asking because you somehow did a mix between all these 3 configurations. Moreover, the DDR1 is configured (both TLB, LAW and Controller) from 0x0, but in the same time you initialized and the SRAM memory from the same address - 0x0. Secondly, the DDR2 LAW is commented, but the DDR Controller is still initialized.
If you really need the all 3 configurations in the same time, try to mix the init_core.tcl file (this will initialize the DDR from 0x0), take the SRAM initialization (L3) from init_sram.tcl file, but re-mapping it from another address - be sure to not be in the same space with DDR (I guess you want to use it as another memory, right?) and if you need and the L1/L2 caches activated take the initialization from init_core_cacheon.tcl file (removes the L3 cache part because you're using it as SRAM).
Thank you,
Marius
Thanks for replying Marius.
So in the absolute the DDR mustn't be interleaved, so DDR1 with 2GB menory space and DDR2 with another 2GB memory space. (DDR2 was desactivated because it wasn't working)
Cache L2 desactivated L1 cache instruction activated and data desactivated.
CPC1 and CPC2 as SDRAM.
This is the configuration that I need.
Actualy I was porting some code and saw that core0 had alot of trouble it crash's with the same error as shown but just before going on a return 0, in the main() when the program was finished.
I started testing ans saw that a simple printf() on the core0 makes it crash.. so I thought it might be related.
normaly DDR1 is from 0x0 to 0x7777_777C
the CPC1 starts at 0x8000_0000 to 0x800F_FFFC
and CPC2 from 0x8010_0000 to 0x801F_FFFC
tested DDR1, CPC1 and CPC2 all worked, I was able to read and write at these adress's.
Can't explain why core0 gets illegal instruction exception.
I'll recheck the TCL.