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IVOR6 0x0700 PROGRAM INTERUPT "illegal instruction exception"

Question asked by Pierre-Antoine Minichetti on Oct 15, 2013
Latest reply on Oct 30, 2013 by Marius Grigoras

Hi,

 

I'm having a strange problem on a P5020 processor.

In fact core0 is generating IVOR6 0x0700 exception "ESR register showing illegal instruction exception" on a simple printf while core1 as no problem running and is on the exact same TLC configuration script.

 

The TCL was modified in ord to use CPC1 and CPC2 as SDRAM.

The DDR controller 1 and 2 are separatly mapped by 2 LAW's each of 2 GB.

 

TLB entries were made for each too.

 

 

/******************************************************************

**************************   MAIN ********************************/

 

int main()

{

    nt i=0;

   

    unsigned long proc_id;

    asm ("mfpir %0" : "=r" (proc_id));

   

#if SMPTARGET

    initSmp();

#endif

   

    printf("Core%d: printf de test !\r\n", proc_id>>5);

    //asm("sc"); // generate a system call exception to demonstrate the ISR

    return 0;

}

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