I am trying to understand one of the intricacies of the DMA peripheral in the MK10DN512V10 4N22D
I have managed to confirm that if a DMA channel is disabled (ERQ bit cleared) then another peripheral cannot request a DMA transfer (i.e. the HRS bit never appears set when debugging and no DMA memory transfer occurs).
It is also easy to confirm that if the START bit is set by software that the DMA transfer does happen even if the DMA channel is 'disabled' (ERQ bit cleared).
The situation I am trying to understand (but have not been able to cause on demand to check) is:
The DMA0 channel is enabled (ERQ0 bit set)
A peripheral requests a DMA channel 0 operation from that channel (HRS0 bit is set) but higher priority channels also waiting on arbitration
The DMA0 channel is disabled by SW (ERQ0 bit cleared) while the DMA0 channel is still pending arbitration (HRS0 bit was set)
The SW immediately attempts to modify the in memory TCD
What happens next:
a) has the HRS0 bit been cleared automatically by the hardware when the ERQ0 bit was cleared?
b) does the DMA0 minor loop execute as soon as arbitration allows it (i.e. ignoring the HRS0 bit), potentially using a corrupt TCD?
c) does the HRS0 bit stay set but no DMA transfer occur until the ERQ0 bit is set once again?
The datasheet does not appear to explicitly say which of a), b) or c) will happen.
I am guessing b) due to the start bit behaviour and some odd wording in the datasheet but I can't confidently test if this is correct.
Does anyone know for certain?