VLPR transition produce reset

[gianlucap_]

Hi,

I'm using KL05Z32, in a project ( solar cell application ) where the energy saving is  important.

I'm using 2 clock configuration: FEI and BLPI and LLS like sleep state.

To test my application I change gradually the voltage from 2.3 to 3.3V while the application run, to simulate the sun.

If PTA7 falling, micro wake-up from LLS and, if there are certain conditions, I change FEI --> BLPI --> RUN --> VLPR to save power.

When micro wake up form LLS I noted that when the voltage exceed 3.08 - 3.1V, any transition to VLPR produce a reset. Micro reset itself every time I try to change in VLPR.

To restore the right condition I must switch off and reduce the voltage (under 3.08 - 3.1V) and switch on the voltage.

If I don't enter in LLS and stay always in RUN, the application run correctly until 3.3V.

(I have another pin electrically connect to PTA7 to sense the interrupt when I am not in sleep state )

Under this voltage it's all right, micro wake-up correctly and the transition to VLPR is correct.

I tried to change in a middle clock configuration: FEI - FBI - BLPI but the problem persist when I change in VLPR.

In FEI core clock is 20Mhz and bus clock is 10Mhz.

In BLPI core clock is 2Mhz and bus clock is 667Khz.

Has anyone had the same problem?

Any solution?

Many thanks

[Kan_Li]

Hi ,

Could you help to confirm below questions:

1. What sample mask is used in this test? I would like to confirm which version is used for this test.
2. Regarding the description “When micro wake up from LLS I noted that when the voltage exceed 3.08 - 3.1V, any transition to VLPR produce a reset”, means customer first wake up MCU from LLS mode, then transition to VLPR mode, if voltage exceed 3.1V, it will reset, right? Could you help to check the clock mode when enter into VLPR mode? is it FEI --> BLPI before enter into VLPR?
3. If it generate reset, could you help to read reset status register to determine which reset type occur?

Thanks for your patience!!

B.R

Kan

[gianlucap_]

The sample mask is 0N96F...

[al_muir]

The 0N96F revision was a pre-production revision that was not publicly available. The issue reported was corrected on the production 1N96F version.

[gianlucap_]

Hi,

1. What do you mean for sample mask? Are you speaking of SIM_SDID information?
2. Yes, when PTA7 falling, MCU first wake-up from LLS. Then, if MCU enter in VLPR when voltage exceed 3.1V, it will reset.

        Yes, before to enter in VLPR I change clock configuration in BLPI with this function" Error = Cpu_SetClockConfiguration(CPU_CLOCK_CONFIG_1)".

        CPU_CLOCK_CONFIG_0 is for FEI...

        I check the value of Error and it is not ERR_RANGE. I set to 1 my debug pin when SMC_PMSTAT == 4 and it is all rigth until voltare is under ~3.1V.

   3. I enabled CPU_ONReset to check which type of reset occurs, but is not none of this: RSTSRC_WAKEUP, LVD, LOC, COP, WDOG, PIN, POR, JTAG,     

       LOCKUP, SW, MDM_AP, SACKERR. 

Many thanks,

[chris_brown]

Gianluca,

I am intrigued by this post.  If the part resets, then can you tell which reset it is?  It has to be some reset source and the reset source will be saved in the Reset Control Module, either in RCM_SRS0 or RCM_SRS1.  Maybe you could try to save the value of these registers into a variable (or maybe the system register file might be better?) before the Processor Expert Initialization?

Thanks,

Chris

[gianlucap_]

Hi Chris,

I understand that the source of reset is LOCKUP.

Have you any ideas?

Thanks,

Gianluca

[zhaohuiliu]

Just a quick suggestion from me for BLPI mode clock configuration,

----------------------------------------------

In BLPI core clock is 2Mhz and bus clock is 667Khz.

----------------------------------------------

1. Reduce bus clock to a even lower speed, may be 333KHz or even lower

2. If #1 is not working, try to lower core clock also to 1MHz or even lower

Maybe the core get wrong instruction from flash, slower the clock may fix it.

Thanks,

Sandy