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JTAG connection problem

Question asked by Tao Wu on Oct 12, 2013
Latest reply on Oct 15, 2013 by Heinz Wrobel

I have used P2020 to bulid up a minium powerpc system then a jtag connection problem came across to me. The system used three LTM4616s as power supply to fulfill 1.05V/1.8V/3.3V power requirement and the power sequencing is according to the HW spec of P2020. The sysclk is 66MHZ provided by GSV1-33VM-66MHz. Some of the power on configurations are realized through logic in the CPLD, and others are thought the pull up/down resistors. The OS is Vxworks 6.8 and I used Workbench as a debug and SDK platform.
It's not a universal phenomenon but appeard in a proportion of circuit board, the phenomenon is described as follow: when the board is power on, and the Workbench simulator jtag is connected. the jtag test process is stopped at stop state. I have tested several signal states: the READY_P0 is asserted and ASLEEP is negated, the LCLK0 of the local bus has output the clock frequency as required. If the powerpc cannot be booted up or jtag connected at one time, it can be booted up or connected through several times of power on/off or power off for a while.
Is there any solution for this problem?