The MM912J637 datasheet states that the current and voltage measurements can be synchronized. The data sheet says this is done by simultaneously enabling the measurements in the ACQ_CTL register (a single write).
I have some simple code that does the following:
ACQ_CTL = 0xFF00; // All measurements off
ACQ_SRH = 0xFF;
ACQ_CTL = 0xFF17; // Enable C, V and internal T measurements and the CVMI interrupt
There are several issues I am seeing:
1) I am getting CVMI interrupts (D2D interrupt with INT_VECT=0x0C) with the lower three bits of ACQ_SRH indicating i) just a current measurement available, ii) just a voltage measurement available and iii) (rarely) both I and V measurement available. So much of the time I see two interrupts where I would expect to see just one.
Why is this?
I did wonder if it was due to subtle race conditions such that skew between the two measurements is enough for an interrupt to be generated and handled by the first ready measurement followed very soon after by the other channel which becomes ready very soon after. However, this does not seem to be the case. If I blip a GPIO pin during interrupt handling the timing between the current-ready interrupt and the voltage-ready interrupt varies wildly between one micro-controller reset and another. This is surprising. It suggest no synch at all between C and V measurements.
What is the full process for ensuring synch between C and V measurements? Do they need to be disabled for some period of time first?
2) Even if I enable just the current measurement (and the CVMI interrupt) I see a second interrupt very close to the first. It appears as though every current measurement generates two interrupts. The second interrupt occurs from about 2us to 10us after the first finishes. Note that this second (very close by) interrupt is *not* the same issue I am talking about in point 1) - there are two seemingly different issues.
CPU is running at 64 MHz and bus clock at 32MHz.
Has anyone got any thoughts about what may be happening?