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MX6Q: SSI1 AUDMUX4: How to change SSI sys clock for sample rate

Question asked by Cerveau stephane on Oct 4, 2013
Latest reply on Oct 22, 2013 by Cerveau stephane

Dear all,

 

I'm trying to connect a codec ( wm8740) through ssi1 and audmux4.

I succeed to connect and play a media with sample rate of 44100 by changing the ssi1_clk to 11289600 but i guess it is not the solution.

My configuration is

unsigned int ptcr, pdcr;
slave = slave - 1;
master = master - 1;
ptcr = MXC_AUDMUX_V2_PTCR_SYN |
MXC_AUDMUX_V2_PTCR_TFSDIR |
MXC_AUDMUX_V2_PTCR_TFSEL(slave) |
MXC_AUDMUX_V2_PTCR_RCLKDIR |
MXC_AUDMUX_V2_PTCR_RCSEL(slave | 0x8) |
MXC_AUDMUX_V2_PTCR_TCLKDIR |
MXC_AUDMUX_V2_PTCR_TCSEL(slave);
pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);
mxc_audmux_v2_configure_port(master, ptcr, pdcr);
ptcr = ptcr & ~MXC_AUDMUX_V2_PTCR_SYN;
mxc_audmux_v2_configure_port(master, ptcr, pdcr);

 

 

ptcr = MXC_AUDMUX_V2_PTCR_SYN |
   MXC_AUDMUX_V2_PTCR_RCLKDIR |
   MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
   MXC_AUDMUX_V2_PTCR_TCLKDIR |
   MXC_AUDMUX_V2_PTCR_TCSEL(master);
pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
mxc_audmux_v2_configure_port(slave, ptcr, pdcr);
ptcr = ptcr & ~MXC_AUDMUX_V2_PTCR_SYN;
mxc_audmux_v2_configure_port(slave, ptcr, pdcr);

In this case i have a MCLK  coming which is SRCK (network_clock) then STCK which is the bitclock and the frame clock.

 

How could i change the MCLK without changing the ssi_clk ? Is there a way to put some divider on this clock ?

 

Any advise ?

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