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CSI Parallel Interface on i.MX6 Dualite

Question asked by KRISHNAPRASADA ALADKA VENKATAKRISHNA on Oct 3, 2013
Latest reply on Oct 3, 2013 by Aven Tsao

Hi

I am using i.MX6 Duallite processor to interface a camera Sensor via its CSI-Parallel Port.

The Camera Sensor requires a Master CLK ( a free running clock) which need to be supplied from the processor.

In turn the Camera output consists of Data Lines [0:9], HSYNC, VSYNC and Pixel clock.

Now the CSI Interface Pin-outs on the i.MX6 Dual Lite shows that the CSI0_MCLK is muxed with CSI0_HSYNC. In this case, what is the suggestion by Freescale community regarding the connectivity of MCLK and HSYNC signals?

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