I am writing a bare metal app for the iMX257 on the PDK board. For a reason I can not understand the eSDHC will not send a complete 48-bit command (CMD-0 with CMDARG=0). Running at under 400 kHz in open-drain mode (with a stable SD_CLK) I see the initial start bit (zero), transmission direction bit (one), then five zero bits (OK so far), then all ones. The SD_CMD line goes back high after the 5th command bit and stays that way. The sixth command bit and all of the 32 command argument bits are high instead of being driven low.
One SD_CLK cycle after the SD_CMD line goes high (6th command bit) the IRQSTAT register indicates 0x0003 0000 (CTOE and CCE are set). The iMX257 reference manual states CCE & CTOE can be set when:
If the eSDHC detects a CMD line conflict when the command is issued. This occurs when the
eSDHC drives the CMD line to 1, but detects a 0 on the CMD line at the next SD_CLK edge. In
this case, the eSDHC aborts the command (stops driving the CMD line), and sets the command
timeout error bit in this register to 1.
I am seeing this, but in reverse as CMD line goes high when it should remain low for the 6th and final command bit and the following 32 argument bits.
There is no MMC or SD card connected to the SD_CLK or SD_CMD lines. I am just monitoring those signals on a scope.
The eSDHC register contents once IRQSTAT changes from 0 to 0x0003 0000 are:
The present state register (PRSSTAT) has the CIHB bit set indicating a command is currently being sent (CMD line in use). This bit never returns back to zero and I can not issue another command unless I reset the entire SDHC peripheral first.
If anybody has some insight as to what I am doing wrong, it would be greatly appreciated.