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QSPI I/03 Diven Low during all Single bit accesses

Question asked by Jon Partee on Sep 18, 2013
Latest reply on Sep 25, 2013 by Edward Karpicz

I the QSPI flash device we are using has a hold feature on I/O pin 3 during all single PAD accesses this pin is being driven low, placing the QSPI device into hold.  The reference manual says these pins are always driven during single pad instructions. and the value driven is taken from QSPI_MCR[ISDnFx] in figure 30-2.  The QSPI-MCR has no definition for these bits.  Another not is for bootmode using QSPI do you drive the IO_3 bit high or low?  Below is the captured image from the reference manual.




Jon Partee