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ANADIG_PLL1_CTRL bit fields

Question asked by Alexandru-Laurentiu Ene Employee on Sep 18, 2013
Latest reply on Oct 3, 2014 by Stefan Agner



I have a question regarding the ANADIG_PLL1_CTRL register from the analog block.

In all reference manual versions (Vybrid Reference Manual, Rev. 6, 08/2013) ANADIG_PLL1_CTRL[DIV_SELECT] is bit 1, but setting that bit will not read back as 1, always as 0.

Instead, ANADIG_PLL1_CTRL[0] seems to be writable.


All other ANADIG_PLLn_CTRL registers seem to behave as described in the manual.


Is PLL1 limited to DIV_SELECT=0 ( X20 ? ) or is there an error in the manual and for PLL1 DIV_SELECT is bit 0 ?