I have a question regarding the ANADIG_PLL1_CTRL register from the analog block.
In all reference manual versions (Vybrid Reference Manual, Rev. 6, 08/2013) ANADIG_PLL1_CTRL[DIV_SELECT] is bit 1, but setting that bit will not read back as 1, always as 0.
Instead, ANADIG_PLL1_CTRL seems to be writable.
All other ANADIG_PLLn_CTRL registers seem to behave as described in the manual.
Is PLL1 limited to DIV_SELECT=0 ( X20 ? ) or is there an error in the manual and for PLL1 DIV_SELECT is bit 0 ?