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Questions about iMX6 parallel display pixel clock limit

Question asked by XJ GAN on Sep 17, 2013
Latest reply on Sep 25, 2013 by Yuri Muhin

     We have a customized imx6q(d) board. To the LCD interface, we found that the larger pixel clock is, more disorder the display will be. This will become obvious when pixel clock goes beyond 40Mhz.

 

     For an example,  we try to attach a LCD to the parallel RGB port. The LCD parameters are 18bpp(rgb666), 720x1280, 60hz, pixel clock is about 57Mhz. According to the data sheet of the LCD, we set proper timing in the kernel source 'mxc_lcdif.c'. But the display seems to be messed enough.

display_60hz.jpg

 

     We captured the signal of the DI0_DISP_CLK (pixel clock of RGB signals), the waveform seems mess too.

wave_form_60hz.jpg

     And then, we set the refresh frequency from 60hz to 30hz (in order to downgrade pixel clock without cropping image). Except the refresh frequency, none of the timing items are changed. Then, the display looks good.

display_30hz.jpg      Again, we captured the signal of the DI0_DISP_CLK (pixel clock of RGB signals), the waveform looks clean.

wave_form_30hz.jpg

 

     We removed LCD from the port, and tried several RGB timing settings with different pixel clocks. Finally, we conclude the result mentioned at the beginning of article. We are using BSP package from 'L3.0.35_1.1.0_121218_source', with patch 03&04 applied. The waveforms of pixel clock are captured from the position most nearby the CPU.

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