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DDR3 routing rules - different signal velocity on inner layers

Question asked by Jakob Unterwurzacher on Sep 13, 2013
Latest reply on Sep 17, 2013 by Yuri Muhin

The signal velocity on internal layers is over 10% slower than it is on outer layers ( http://www.altera.com/literature/an/an224.pdf figure 9). The difference is so big that if you ignore it, you may end up actually violating the allowed length differences (as stated in the HDG) by far.

Still, the fact that the signal propagates slower on the inner layers seems to never be mentioned in the IMX6 documentation.

What's going on here? Will the error just be absorbed by the safety factors?

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