We are able to change the RAS to CAS delay by changing TRCD_INT in CTL41 from 3 to 7.
We were NOT able to change the write latency (WRLAT) or cas latency (CLAT) from its default value of 3 and 4 respectively. In the .maj file from Mentor, the default value of CTL37 is 0x7080403. We tried values for the WRLAT field from 1 to 7, and the register reads back as having changed, but there was no change in the waveform. Here are the steps:
- 1. Change CTL37 in .maj file.
- 2. Program the code into the processor using emulator.
- 3. Check for the change in the waveform (time difference between center of Chip select/write select signal to falling edge of DQS_N) using oscilloscope.
These were performed using the EVK.
Wondering if this problem is specific to the Mentor Nucleus tool chain. Has anyone else had success updating the WRLAT and CLAT parameters?