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Request for Clarification on SPI clk

Question asked by n00b1024 on Sep 9, 2013
Latest reply on Sep 10, 2013 by Naoum Gitnik



I'm working with SPI on the VF60 (Vybrid), and am trying to find out the max frequency that the SPI can run at. According to the RM, the maximum SPI clock frequency is half the system clock (spi_clk = sys_clk*(1+DBR)/(PBR*BR), where DBR = 1, PBR = 2, BR = 2, cf. Section 47.4.3, Vybrid Reference Manual rev5). When the RM talks about the "system clock," what is it referring to? Is that the IPS clock frequency, or the Platform Bus clock? There's a note on page 630 (Sec 9.12) that says that the max baud rate for the SPI output is 83 MHz.


Also, Table 9-10 says that the max IPG (output) frequency is 85 MHz, while Table 9-5 says that the max IPG frequency is 83 MHz.


Thanks much!