AnsweredAssumed Answered

Using RGMII compatible PHY with i.MX6 (u-boot)

Question asked by Tomasz Nowak on Sep 9, 2013
Latest reply on Sep 16, 2013 by Yuri Muhin

On our board we would like to use a RGMII-PHY together with i.MX6DL.

 

The MAC and PHY are connected similiar to the SABRE reference board, the main difference is that the ENET_REFCLK pin which is not connected at all.

I assume this is OK, according to the "Hardware Development Guide" (chapter 12.3 Generating the reference clock) "the pin labeled “ENET_REF_CLK” in Figure 12-2 is only required by the full MII interface.

It is not used by the RMII interface."

 

Based on this I made further customization (compared to the "sabre-sd" board configuration):

* setting bit ENET_CLK_SEL in GPR1

* configuring (internal) ENET PLL to generate ethernet reference clock (125Mhz),

 

Unfortunatelly u-boot fails to ping another host, I'm getting "TX timeout packet" error. I suppose this could be caused by missing reference clock.

I checked already that management interface to the PHY works but the RGMII_TXC line doesn't show any activity (during ping command).

 

Did anybody encounter similiar problems?

Is it possible to route ENET PLL to ENET_REF_CLK (internally - using IOMUX) or does it have to be routed externally (i.e. from GPIO16 or PHY generating 125Mhz)?

 

Thank you for any feedback

Outcomes