area : 19–16 PHYCTL_DL
Please tell me how to set this register.
After Leveling, and is set automatically?
this is related to clock de-assertion and assertion, like when you go to low power modes.
So, The timing for sending the power-down or self-refresh command and the timing for disabling the clock are independent and unrelated, and therefore a situation could occur in which the clock is disabled before the power-down or self-refresh command has been sent. This could be catastrophic for memory data
So for this parameter, consider if you are using low power modes where you need your memory to be kept on self refresh mode. If yes, you need to check how many cycles are required for sending a self-refresh command or a power-down command and use that timing.
Retrieving data ...