Please tell me the timing chart set by these.
Hi Keisuke Watanabe
Sorry, we don't have time diagrams for this signals but I can provide some more data on this signals and how/when to configure.
This parameter works together with Gate_cfg (see this) it modifies the same internal signal in the phy controller. Similarly, typically will be set to zero and adjusted when there are read fails (probably related to PCB delays)
The DQS signal is generated based on the CLK reference internally. This parameter tells if DQS should be delayed half cycle or not. Typically there is no need to adjust this parameter since the data is already adjusted respect to DQS properly with the DLL_WRITE_DL in PHY04
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