Steve Melnikoff

SPI interrupt not triggering (MC9S12DG256 + CW 3.1)

Discussion created by Steve Melnikoff on Jul 24, 2007
Latest reply on Apr 21, 2008 by Jim Donelson
Hi.
 
I'm in the process of porting some code from a DG128 to a DG256. After making the minimum number of changes (mainly relating to the differences in the memory map), the code does run. However, I've found that the SPI interrupt doesn't trigger.
 
This worked fine on the DG128. The only clue I could find in the documentation was the fact that the SPI module has been upgraded in the DG256, such that "In SPI Master Mode, the change of a config bit during a transmission in progress, will abort the transmission and force the SPI into idle state."
 
The code doesn't change any configuration bits during a transmission. However, there are circumstances where the SPIE bit is cleared or set during transmission. The assembly produced by the compiler uses BSET/BCLR, which I assumed wouldn't affect any of the other bits. Is this assumption wrong?
 
I've experimented with the debugger, with some odd results:
  1. Single stepping through the code which writes to SPIDR sets SPIF as expected, but then clears SPIF on the next instruction, even if the next instruction is a NOP! (I understand from another post that the debugger reading the SPI registers could cause this flag to be cleared).
  2. Specifying a particular register in the watch window, then restarting the code, makes the problem go away! The following registers worked: SPISR, SPICR1, SPICR2, and an I2C register; SPIDR did not. It didn't matter whether the memory or watch windows were open or not.
  3. It makes no difference whether the BDM module is connected or not.

All in all, this is a bit of a puzzle, especially as this code worked fine on the DG128. I would welcome any suggestions!

Steve.

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