I2S RX master mode, 44.1k , but the MCLK, RX_BCLK, RX_FS are not output, no wave. the below is the configure. How can i do?
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void I2S_Init(void)
{
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable SSI clock in SIM */
// At first Disable system clock to the I2S module
SIM->SCGC6 &= ~(SIM_SCGC6_I2S_MASK);
SIM->SOPT2 |= SIM_SOPT2_I2SSRC(0); //I2S clock source is system clock
// divide clock source to I2S module to generate desired frequency
// 48kHz
//SIM_CLKDIV2 |= SIM_CLKDIV2_I2SDIV(7) | SIM_CLKDIV2_I2SFRAC(0);
// Divide to get the 11.2896 MHz from 96MHz
// for 44.1 kHz
SIM->CLKDIV2 |= SIM_CLKDIV2_I2SDIV(16) | SIM_CLKDIV2_I2SFRAC(1);
// enable system clock to the I2S module
SIM->SCGC6 |= SIM_SCGC6_I2S_MASK;
/* enable SSI pins */
PORTE->PCR[6] = PORT_PCR_MUX(0x04); // configure port for MCLK output
//GPIO for SSI0_RX_BLCK
PORTE->PCR[9] = PORT_PCR_MUX(0x04); //
//GPIO for SSI0_RX_FS
PORTE->PCR[8] = PORT_PCR_MUX(0x04); //
//GPIO for SSI0_RXD
PORTE->PCR[7] = PORT_PCR_MUX(0x04); //
/* Issue a SSI reset (bit 0 of I2S_CR */
I2S0->CR &= ~I2S_CR_SSIEN_MASK;
// initialize I2S Control Register (I2S_CR)
// note reset values are all zero
I2S0->CR =0
| I2S_CR_I2SMODE(1) // Set I2S master mode
//| I2S_CR_I2SMODE(2) // Set I2S slave mode
| I2S_CR_SYSCLKEN_MASK // Set clock out on SSI_MCLK pin
| I2S_CR_SYN_MASK // Enable synchronous mode
//| I2S_CR_NET_MASK // Enable network mode
| I2S_CR_RE_MASK // Enable the receive section, this does not enable interrupts
//| I2S_CR_TE_MASK; // Enable the transmit section, this does not enable interrupts
//| I2S_CR_TCHEN_MASK // Enable two channel mode
;
I2S0->RCR = 0
//| I2S_RCR_RXEXT_SHIFT
//| I2S_RCR_RXBIT0_SHIFT
//| I2S_RCR_RFEN1_SHIFT // RX FIFO 1 enable
| I2S_RCR_RFEN0_SHIFT // RX FIFO 0 enable
| I2S_RCR_RFDIR_SHIFT
| I2S_RCR_RXDIR_SHIFT
//| I2S_RCR_RSHFD_SHIFT
| I2S_RCR_RSCKP_SHIFT
| I2S_RCR_RFSI_SHIFT
//| I2S_RCR_RFSL_SHIFT
//| I2S_RCR_REFS_SHIFT
;
I2S0->RCCR = 0
| I2S_RCCR_WL(0x7) // 16 bit word length
| I2S_RCCR_DC(1) // Frame rate divider
| I2S_RCCR_PM(3);
I2S0->FCSR = 0
| I2S_FCSR_RFWM0(2)
| I2S_FCSR_RFWM1(2)
;
// initialize I2S Interrupt Enable Register (I2S_IER)
I2S0->IER = 0 /* interrupts */
//| I2S_IER_TIE_MASK /* turn on transmit interrupts */
//| I2S_IER_TDE0EN_MASK /* turn on transmit data 0 empty */
//| I2S_IER_TDE1EN_MASK /* turn on transmit data 1 empty */
//| I2S_IER_TFE1EN_MASK /* turn on transmit frame 1 empty */
//| I2S_IER_TFE0EN_MASK /* turn on transmit frame 0 empty */
//| I2S_IER_RIE_MASK /* turn on receive interrupts */
//| I2S_IER_RDR0EN_MASK /* turn on receive data 0 full */
//| I2S_IER_RDR1EN_MASK /* turn on receive data 1 full */
//| I2S_IER_TDMAE_MASK /* DMA request enabled */
//| I2S_IER_RDMAE_MASK
;
/* enable i2s */
I2S0->CR |= I2S_CR_SSIEN_MASK;
}
