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Lowest Cost Boot Design ?

Question asked by ChrisNielsen on Aug 26, 2013
Latest reply on Apr 18, 2014 by Alec Cohen

I'm designing for a very cost sensitive application.  I was planning to use low-end SPI NOR FLASH as my boot/storage device with no DDR external memory -- the on-board RAM (1MB) is sufficient for my data needs and my code will fit completely in the 512 KB cache.

 

The issue is that with "load and go" approach, I "waste" ~512KB of precious on-board RAM for my code's initial execution location which is useless since it is quickly pulled into cache and the 512 KB of RAM is never accessed again and I am left with 512 KB of RAM data space as opposed to a full 1 MB if I could execute in place (XIP).

 

>>> Or, is there a trick where I can lock all my code into cache then recover the 512 KB of initial code location and reuse it as data RAM?

 

So, I am studying all XIP options.  I only see two listed: 1) Quad SPI, 2) Parallel NOR FLASH on FlexBus.

 

1) Quad SPI.  My concern here is whether or not it is possible to boot from a single 4-bit wide (quad) SPI device.  RM Table 19-9 seems to imply that two devices are required and the fact that the Tower board has two adds to my concern.

 

>>> So...is it possible to XIP from a single 4-bit SPI device?

 

Spansion S25FL032P is one example of a low-cost (<$0.60 @ 1K) quad SPI part that I am considering.

 

Thanks, Chris

 

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