Austin Appleby

KL0 power consumption @ 4 mhz - 3x higher than expected.

Discussion created by Austin Appleby on Aug 24, 2013
Latest reply on Aug 27, 2013 by Austin Appleby

I'm doing some basic power consumption tests on a MLK05Z32 chip and am seeing much higher power consumption than expected - with a 4 mhz system clock (fast internal reference clock, FLL disabled) and 2 mhz bus clock (OUTDIV4=1), the chip is drawing about 1.5 milliamps in a simple LED blink test. That's about 3x the draw of the competitor's chip with the same clocks & code - rather disappointing.


I'm looking for ways to reduce the power draw, but not having much luck - the application I'm evaluating the chip for will require some cycle-accurate bitbanging, so I don't think VLPR mode will work for me as the 0.8 mhz flash clock in that mode slows things down whenever there's an instruction cache miss.


Are there any other ways to reduce the power draw that I'm missing? I need deterministic 4 mhz operation, no wait states.