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MK10 clock issues

Question asked by mrandreas on Aug 23, 2013
Latest reply on Aug 26, 2013 by mrandreas

My target is an MK10FN1M0VLQ12. I’ve tried using two clock options; a 25 Mhz oscillator to XTAL0 ->PLL0 with a 100Mhz and 60Mhz and the internal clock with 41,943Mhz.

I have measured the TRACE_CLKOUT at PTA6:

SIM->SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK

SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;

PORTA-> PCR[6] = PORT_PCR_MUX(0x7) | PORT_PCR_DSE_MASK;

 

The Trace_CLKOUT shall be half of the core clock.

 

When the external clock is configured to 100Mhz the Trace_CLKOUT is 25MHz.

When the external clock is configured to 60Mhz the Trace_CLKOUT is 15MHz.

Also when the internal clock is configured to 41,943… Mhz the Trace_CLKOUT is 10.333MHz.

 

The external clock configuration:

25Mhz * (VDIV=24/ PRDIV=3)/2  = 100 Mhz and 25Mhz * (VDIV=24/ PRDIV=5) / 2 = 60Mhz

 

What is wrong with? My Uart gives me only gurba. When configuring the UART BDL (baud rate) according to measured value the UART gives me gurba as well. I’m using the KEIL ide.

 

Anny Idea what causing me this headache?

 

Internal CLK Config:

 

/* SIM_SCGC5: PORTA=1 */

  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */

  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */

  /* SIM_SOPT2: PLLFLLSEL=0 */

  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */

  /* SIM_SOPT1: OSC32KSEL=0 */

  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */

  /* SIM_SCGC1: OSC1=1 */

  SIM->SCGC1 |= (uint32_t)0x20UL;

  /* PORTA_PCR18: ISF=0,MUX=0 */

PORTA->PCR[18] &= (uint32_t)~0x01000700UL;

  /* Switch to FEI Mode */

  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */

  MCG->C1 = (uint8_t)0x06U;

  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */

  MCG->C2 = (uint8_t)0x20U;

  /* MCG_C4: DMX32=0,DRST_DRS=1 */

  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);

  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC0->CR = (uint8_t)0x80U;

  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC1->CR = (uint8_t)0x80U;

  /* MCG_C7: OSCSEL=0 */

  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;

  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */

  MCG->C5 = (uint8_t)0x00U;

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */

  MCG->C6 = (uint8_t)0x00U;             /* 3 */

  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */

  MCG->C11 = (uint8_t)0x00U;            /* 3 */

  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */

  MCG->C12 = (uint8_t)0x00U;            /* 3 */

 

 
 

 

External CLK config:

 

/* SIM_SCGC5: PORTA=1 */

  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */

  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  SIM->CLKDIV1 = (uint32_t)0x01330000UL; /* Update system prescalers */

  /* SIM->SOPT2: PLLFLLSEL=1 */

  SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */

  /* PORTA_PCR18: ISF=0,MUX=0 */

  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;

  /* Switch to FBE Mode */

  /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC0->CR = (uint8_t)0x00U; /* ????????????????????????????? */

  /* MCG->C7: OSCSEL=0 */

  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;                          

  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */

  MCG->C2 = (uint8_t)0x24U;                            

  /* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG->C1 = (uint8_t)0xA8U;                            

  /* MCG->C4: DMX32=0,DRST_DRS=0 */

  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;                          

  /* MCG->C5: PLLREFSEL0=0,PLLCLKEN0=1,PLLSTEN0=0,??=0,??=0,PRDIV0=1 */

  MCG->C5 = (uint8_t)0x02U;//DIV3                            

  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=16(32) */

  MCG->C6 = (uint8_t)0x08U;//multi24                            

  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

  }

  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

  }

  /* Switch to PBE Mode */

  /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */

  MCG->C6 = (uint8_t)0x48U;                            

  while((MCG->S & MCG_S_PLLST_MASK) != MCG_S_PLLST_MASK) {    /* Wait until source of PLLS is PLLCS output clock */

  }

  while((MCG->S & MCG_S_LOCK0_MASK) != MCG_S_LOCK0_MASK) { /* Wait until PLL locked */

  }

  /* Switch to PEE Mode */

  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCG->C1 = (uint8_t)0x28U;                            

  while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_MASK) {    /* Wait until output of the PLL is selected */

  }

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